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% File: summary.tex
% Author: Mike Bolotski (misha@ai.mit.edu)
% Copyright (C) Artificial Intelligence Laboratory, 1996
%*-------------------------------------------------------------------------
%*
%* HISTORY:
%* Last edited: May 29 16:22 1996 (misha)
%* Created: Mon Mar 18 20:23:21 1996 (misha)
%*-------------------------------------------------------------------------

\chapter{Summary}

Reconfiguration is the ability to dynamically configure memory
organization, ALU width, or communication network topology to match the
needs of the computational problem.  {\em Parallel computers based on
reconfigurable bit-slice architectures can be an order of magnitude faster
on important applications than those based on conventional architectures}.
This dissertation will validate the thesis with an implementation-based
approach.

The proposed research will develop a reconfigurable architecture optimized
for high speed VLSI, complete an aggressive implementation of the
architecture, and evaluate the performance on a standard computer vision
benchmark suite.  Parameters from the implementation will be used to
investigate an analytical performance model.  The existence of a concrete
instantiation of the architecture will allow empirical evaluation of the
costs and benefits of reconfiguration.

%Reconfigurable computing, the ability for ALUs to function at different
%word widths, has been around for some time.  The advantages of flexibly
%varying the word width have been demonstrated by a number of researchers.
%However, this research has been inadequate because it hasn't addressed a
%number of key issues: the true hardware costs of reconfiguration, the
%constraints of high-speed operation, and the performance on real
%applications. 

% This thesis aims to fill in these gaps by developing a
%reconfigurable architecture optmized for high speed VLSI, completeing an
%aggressive implementation of the architecture, executing a standard
%computer vision benchmark suite on a simulator, deriving an analytical
%model of the performance, with the parameters obtained from the hardware
%and software implementations.\footnote{The main approach is to {\bf
%    implement}}.  

%This thesis investigates the design of a high-performance parallel SIMD
%system designed for low-precision integer operations.  The hypothesis
%underlying the research is that a reconfigurable bit-slice approach can be
%substantially more efficient than conventional bit-serial organizations and
%more flexible than hardware bit-parallel.  Preliminary support for this
%conclusion has been obtained from  a simplified model of hardware
%and algorithms.  The goal of the remaining work is to confirm the
%conclusion by:

Much of the research is already complete. A chip incorporating 1024
processors and designed to operate at 125 MHz has been fabricated. The
processor array has been tested at up to 80~MHz and is expected to achieve
the design target.  Vision algorithms from the DARPA Image Understanding
benchmark have been coded at a parallel assembler level. A preliminary
performance model has been developed. The remaining tasks are:

\begin{itemize}

\item complete testing of external chip interfaces.
\item implement a simulator for the architecture
\item use the vision benchmark instruction traces from the simulator to make detailed
  architectural evaluations
\item validate the an analytical performance model 
\item design a second-generation architecture that builds on the lessons
  of the initial implementation, with an eye to technology trends.

\end{itemize}

The organization of the thesis (and of the proposal) essentially follows
the outline presented above.

\begin{enumerate}
\item {\bf Introduction and Motivation.}  Describes the
computational requirements of early vision and some parallel processing
approaches to achieving these requirements.

\item {\bf Previous and Related Work.}
There is a substantial body of previous work relating to the topics of this
thesis, from SIMD machines to modern architectural alternatives: the SRC
PIM chip, Berkeley's PADDI-2 DSP, and FPGA based computing platforms.
After the architectural discussion, this chapter evaluates related
analytical performance models.

\item {\bf Reconfigurable Bit-Parallel Architecture.} Describes
in detail the motivations for an RBP organization, RBP arithmetic
algorithms, and specifics of the Abacus design.


\item {\bf The Abacus-1 Chip and System.} Describes the implementation of
  the Abacus-1 chip at a fairly detailed level, as well as chip test
  results.  Also describes the issues of a high-speed SIMD machine and
  presents a relatively detailed design of the Abacus computer, including
  I/O and control issues.


\item {\bf Parallel Vision Algorithms.}  Describes a set of vision and
communication algorithms chosen both for application value and for
architectural evaluation. These algorithms include several from the DARPA
Image Understanding Benchmark suite. Discusses the performance of Abacus on
these algorithms.  

%\item {\bf  Reconfigurable Mesh: Algorithms And Limitations.}
%This unrelated chapter describes the algorithmic improvements to mesh
%algorithms based on the RMESH machine model. It evaluates the match of real
%VLSI technology to the model and practical speedups on Abacus.

\item {\bf Architectural Tradeoffs.} Evaluates architectural
tradeoffs such as local memory size, ALU width, off-chip memory bandwidth
and network bandwidth based on instruction traces from the parallel
algorithms. 

\item {\bf The Next Generation: Abacus-2.}  Describes a set of
modifications that allow a redesigned Abacus element to function in
multiple-SIMD mode, as a systolic processor, or to emulate random logic
circuits effectively.

\item {\bf Conclusions.}  The contents of this chapter will
depend (somewhat) on the results of the actual research.
\end{enumerate}


\subsection*{Schedule}

%% %\begin{table}
\begin{center}
\begin{tabular}{|l|l|l|l|}
\hline
Task & Time & Start & End  \\
\hline
Simulator coding         & 14 & Mar 30 & Apr 12  \\
\hline
Chip testing             & 12  & Apr 13  & Apr 27  \\
\hline
Architectural analysis   & 14 & May 2 & May 16  \\
\hline
Text writing             & 28 & May 17 & Jun 17  \\
\hline
\end{tabular}
\end{center}
%%%\end{table}

%% \subsection*{Notes}



%{

%\small
%\begin{itemize}

%\item Need to provide a hard model.
%\item Encounter system level issues.
%\item Already discovered that off-chip memory references are the dominant
%  factor.
%\item Empirical evaluation of the costs of flexibility.
%\item Concrete instationation of architecture type.
%\item Obtain reasonable limits on communication time.
%\item Incorporate overhead of reconfiguration time.

%\item Benefit is eacy, but cost analysis requires silicon area and
%  execution time estimates.
%\item Research answer question of ``what does flexibility get you and how
%  much does it cost?''.

%\item To fully answer the question, need to push limits of implementation.
%\end{itemize}

%}

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