Summary

Reconfiguration is the ability to dynamically configure memory organization, ALU width, or communication network topology to match the needs of the computational problem. Parallel computers based on reconfigurable bit-slice architectures can be an order of magnitude faster on important applications than those based on conventional architectures. This dissertation will validate the thesis with an implementation-based approach.

The proposed research will develop a reconfigurable architecture optimized for high speed VLSI, complete an aggressive implementation of the architecture, and evaluate the performance on a standard computer vision benchmark suite. Parameters from the implementation will be used to investigate an analytical performance model. The existence of a concrete instantiation of the architecture will allow empirical evaluation of the costs and benefits of reconfiguration.

Much of the research is already complete. A chip incorporating 1024 processors and designed to operate at 125 MHz has been fabricated. The processor array has been tested at up to 80 MHz and is expected to achieve the design target. Vision algorithms from the DARPA Image Understanding benchmark have been coded at a parallel assembler level. A preliminary performance model has been developed. The remaining tasks are:

• complete testing of external chip interfaces.

• implement a simulator for the architecture

• use the vision benchmark instruction traces from the simulator to make detailed architectural evaluations

• validate the an analytical performance model

• design a second-generation architecture that builds on the lessons of the initial implementation, with an eye to technology trends.

The organization of the thesis (and of the proposal) essentially follows the outline presented above.

1. Introduction and Motivation. Describes the computational requirements of early vision and some parallel processing approaches to achieving these requirements.

2. Previous and Related Work. There is a substantial body of previous work relating to the topics of this thesis, from SIMD machines to modern architectural alternatives: the SRC PIM chip, Berkeley’s PADDI-2 DSP, and FPGA based computing platforms. After the architectural discussion, this chapter evaluates related analytical performance models.

3. Reconfigurable Bit-Parallel Architecture. Describes in detail the motivations for an RBP organization, RBP arithmetic algorithms, and specifics of the Abacus design.

4. The Abacus-1 Chip and System. Describes the implementation of the Abacus-1 chip at a fairly detailed level, as well as chip test results. Also describes the issues of a high-speed SIMD machine and presents a relatively detailed design of the Abacus computer, including I/O and control issues.

5. Parallel Vision Algorithms. Describes a set of vision and communication algorithms chosen both for application value and for architectural evaluation. These algorithms include several from the DARPA Image Understanding Benchmark suite. Discusses the performance of Abacus on these algorithms.

6. Architectural Tradeoffs. Evaluates architectural tradeoffs such as local memory size, ALU width, off-chip memory bandwidth and network bandwidth based on instruction traces from the parallel algorithms.

7. The Next Generation: Abacus-2. Describes a set of modifications that allow a redesigned Abacus element to function in multiple-SIMD mode, as a systolic processor, or to emulate random logic circuits effectively.

8. Conclusions. The contents of this chapter will depend (somewhat) on the results of the actual research.

Schedule

Task  Time Start  End
Simulator coding  14  Mar 30 Apr 12
Chip testing  12  Apr 13 Apr 27
Architectural analysis 14  May 2 May 16
Text writing  28  May 17 Jun 17