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% Author: Mike Bolotski (misha@ai.mit.edu)
% Copyright (C) Artificial Intelligence Laboratory, 1996
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%* Last edited: Mar 19 16:05 1996 (misha)
%* Created: Mon Mar 18 20:23:21 1996 (misha)
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\section*{Executive Summary}

%{\em This is the BS-free version of the document. It will no doubt be
%  cleaned up for official presentation.}

This thesis investigates the design of a high-performance parallel SIMD
system designed for low-precision integer operations.  The hypothesis
underlying the research is that a reconfigurable bit-slice approach can be
substantially more efficient than conventional bit-serial organizations and
more flexible than hardware bit-parallel.  Preliminary support for this
conclusion has been obtained from  a simplified model of hardware
and algorithms.  The goal of the remaining work is to confirm the
conclusion by:

\begin{itemize}
\item designing and testing a high performance chip,
\item completing a (paper) system-level design that will allow the chips to operate
  at a high sustained rate,
\item implementing a number of SIMD algorithms on a simulator to
  demonstrate performance on real applications,
\item using the instruction traces from the algorithms to make detailed
  architectural evaluations and comparing simulation results to an
  analytical model,
\item designing a second-generation architecture that builds on the lessons
  of the initial implementation, with an eye to technology trends.
%\item evaluating the impact of technology trends on this architectural
%  family.
\end{itemize}

The organization of the thesis (and of the proposal) essentially follows
the outline presented above.

\paragraph{Chapter 1: Introduction and Motivation.}  Describes the
computational requirements of early vision and some parallel processing
approaches to achieving these requirements.

\paragraph{Chapter 2: Previous and Related Work.}
There is a substantial body of previous work relating to the topics of this
thesis, from SIMD machines to modern architectural alternatives: the SRC
PIM chip, Berkeley's PADDI-2 DSP, and FPGA based computing platforms.
After the architectural discussion, this chapter evaluates related
analytical performance models.

\paragraph{Chapter 3: Reconfigurable Bit-Parallel Architecture.} Describes
in detail the motivations for an RBP organization, RBP arithmetic
algorithms, and specifics of the Abacus design.


\paragraph{Chapter 4: The Abacus-1 Chip.} Describes the implementation of
the Abacus-1 chip at a fairly detailed level, as well as chip test results.

\paragraph{Chapter 5: System-Level Issues of a High-Speed SIMD Machine.}
Describes the issues of a high-speed SIMD machine and presents a
relatively detailed design of the Abacus computer, including I/O and
control issues.


\paragraph{Chapter 6: Parallel Vision Algorithms.}  Describes a set of vision and
communication algorithms chosen both for application value and for
architectural evaluation. These algorithms include several from the DARPA
Image Understanding Benchmark suite. Discusses the performance of Abacus on
these algorithms.  

%\paragraph{Chapter 7:  Reconfigurable Mesh: Algorithms And Limitations.}
%This unrelated chapter describes the algorithmic improvements to mesh
%algorithms based on the RMESH machine model. It evaluates the match of real
%VLSI technology to the model and practical speedups on Abacus.

\paragraph{Chapter 7: Architectural Tradeoffs.} Evaluates architectural
tradeoffs such as local memory size, ALU width, off-chip memory bandwidth
and network bandwidth based on instruction traces from the parallel
algorithms. 

\paragraph{Chapter 8: The Next Generation: Abacus-2.}  Describes a set of
modifications that allow a redesigned Abacus element to function in
multiple-SIMD mode, as a systolic processor, or to emulate random logic
circuits effectively.

\paragraph{Chapter 9: Conclusions.}  The contents of this chapter will
depend (somewhat) on the results of the actual research.


\subsection*{Schedule}

%% %\begin{table}
\begin{center}
\begin{tabular}{|l|l|l|l|}
\hline
Task & Time & Start & End  \\
\hline
Test board fabrication   & 21 & Sep 11 & Oct 1  \\
Test board assembly      & 3  & Oct 1 & Oct 4   \\
Test board/C30 interface & 3  & Oct 5 & Oct 7   \\
Test vector design       & 5  & Oct 8 & Oct 12    \\
Chip testing             & 7  & Oct 13 & Oct 19  \\
\hline
{\bf Area Exam}           & 30 & Oct 15 & Nov 15 \\
\hline
%% Simulator spec  &  2 & Nov 15 & Nov 17  \\
Simulator coding         & 14 & Nov 17 & Dec 1  \\
Architectural analysis   & 21 & Dec 1 & Dec 22  \\
\hline
Text writing             & 30 & Dec 22 & Jan 12  \\
Thesis defense           & 7 & Jan 13 & Jan 20 \\
\hline
\end{tabular}
\end{center}
%%%\end{table}


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