
		The M-Machine Multicomputer

Advances in VLSI technology have resulted in computers with chip area
dominated by memory and not by processing resources.  The normalized
area of a VLSI chip is increasing by 50% per year, while gate speed
and communication bandwidth are increasing by 20% per year.  As a
result, a 64-bit processor with a pipelined FPU is only 8% of a 1996
0.35um chip.  In a system with 256 MBytes of DRAM, the processor
accounts for only 0.13% of the silicon area in the system.  The memory
system, cache, TLB, controllers, and DRAM account for most of the
remaining area.  Technology scaling has made the memory, rather than
the processor, the most area-consuming resource in a computer system.

This talk presents the MIT M-Machine, an experimental multicomputer
being designed and built to test architectural concepts motivated by
the constraints of modern semiconductor technology and the demands of
programming systems.  The M-Machine computing nodes are connected with
a 3-D mesh network; each node consists of a custom 13 million
transistor Multi-ALU processor (MAP chip) and 8 MBytes of off-chip
synchronous DRAM.  The multithreaded MAP chip incorporates 12 function
units, an interleaved on-chip cache, network interface, and a 3-D
dimension ordered router.  The execution resources on the MAP chip
comprise 32% of the chip area and 11% of 8MB node.  For a 256MB system
the M-Machine's peak performance/area is 85 times better than today's
microprocessor based systems at only 50% more silicon area cost.  Even
at a small fraction of this peak performance, such a machine allows
the costly, fixed-sized memory to handle more problems per unit time
resulting in more cost-effective computing.


The multiple function units are used to
exploit both instruction-level and thread-level parallelism.  A user
accessible message passing system yields fast communication and
synchronization between nodes.  Rapid access to remote memory is
provided transparently to the user with a combination of hardware and
software mechanisms.



To address this imbalance, the \mm\ increases the fraction of chip
area devoted to processor, making better use of the critical memory
resources.  

TheAn \mm\ multi-ALU processor (\MAP ) chip contains four
64-bit three-issue {\em clusters} that comprise 32\% of the
5G$\lambda^2$ chip and 11\% of an 8~MByte (six-chip) node.  

The
multiple execution clusters will provide better peak performance than
using a single cluster and a large on-chip cache in the same chip
area.  The high ratio of arithmetic bandwidth to memory bandwidth (12
operations/word) allows the \MAP\ to saturate the costly DRAM
bandwidth even on code with high cache-hit ratios.  A 32-node \mm\
system with 256~MBytes of memory has 128 times the peak performance of
a 1996 uniprocessor with the same memory capacity at 1.5 times the
area, a 85:1 improvement in peak performance/area.  Even at a small
fraction of this peak performance, such a machine allows the costly,
fixed-sized memory to handle more problems per unit time resulting in
more cost-effective computing.


This talk will focus on the unique mechanisms of the MAP chip, the
compilation model for executing code on a single node, and on some
implementation issues that arise when building a large, complex
chip in a university environment.
