//***********************************************************************
//* README/INDEX FOR FPU RELEASE 990401	                        	*
//*                                                                     *
//* Stanford CVA group:      M-Machine Project                          *
//*                                                                     *
//* Author: Andrew Chang                                                *
//*                                                                     *
//*     990401          Created         Andrew Chang                    *
//*                                                                     *
//* Description:                                                        *
//*                                                                     *
//*     This directory contains the RTL source files for the M-Machine  *
//*     Floating Point Execution Unit					*
//*                                                                     *
//* Copyright (C) 1994, 1995, 1996, 1997, 1998, 1999                    * 
//*                                                                     *
//* Stanford University							*
//* Concurrent VLSI Architecture Group                                  *
//* All rights reserved                                                 *
//*                                                                     *
//***********************************************************************
 

OVERVIEW
********


	This release includes the source code for the M-Machine's 64b Floating
	Point Unit (FPU).  The FPU contains three sub-units: Multiply-Add 
	(MULA) pipeline, Divide/Square-Root (DSQ) and a Network Communication
	Unit (SENDC).	The FPU is IEEE-754 format compatible and implements
	a SUBSET of the other IEEE features.

	The complete source code for the behavioral model is provided.
	However, this source code will NOT simulate as is since it requires
	a custom M-Machine scripts, environment and tool infrastructre.  So,
	to facilitate exploration of the code,  four standalone test cases 
	are provide which can be simulated directly with the provided 
	M-Machine specific verilog executable.

	

DIRECTORY
*********


mm/rtl/map/fpu/RELEASE/
		
		*.v		The actual behavioral Verilog files

		fpu_top.cmd	A M-Machine specific format include
				file - lists all the files required to
				compile and simulate the FPU.

		fpu.stim	Stimulus/test file for the FPU.  Includes
				various settings and options actuated by
				comment/uncommenting lines of code.


		BIN/		Includes the M-Machine version of the
				verilog executable - includes custom PLI
				routines:		

				verilog*

		DECOMPILED/	Includes four (4) runnable test simulations
				of the FPU.

				usage:

				    ../BIN/verilog  <filename>.dv

				  
				Notes:   You MUST use the M-Machine verilog
					 Each of the tests will report some
					  errors as the M-Machine FPU is
					  NOT fully IEEE compliant.

					 <filename>.dump.fast are the
					 corresponding dump files for
					 each simulation in the UNDERTOW
					 binary format.
			
		RCS/		All .v files are under RCS

		TESTVECTORS/	Contains the four (4) sets of testvectors which
				can be selected in the .stim file

		UNDERTOW/	Contains fpu_check.env which loads a basic set
				of Undertow environment variables.
						
		dsq/		Contains more, potentially out-of-date DSQ
				documentation.

		mula/		Contains more, potentially out-of-date MULA
				documentation.

mm/rtl/map/fpu/doc		Overall FPU documentation - note some of this
				is out-of-date

mm/rtl/map/fpu/dsq_doc		Documentation for the divide-square-root logic
				- note some of this is out-of-date

mm/rtl/map/fpu/mula_doc		Documentation for the multiply-add unit
				- note some of this is out-of-date


mm/rtl/map/map.vhout		Verilog "header file" contains values
				for GLOBAL-level design "constants" and
				parameters

mm/rtl/map/clst/clst.vhout	Verilog "header file" contains values
				for CLUSTER-level design "constants" and
				parameters


mm/rtl/lib/			This directory hierarchy contains the
				verilog models for miscellaneous library
				cells used throughout the M-Machine design.
				Only a subset of these are used in the FPU.
				Standard cells, datapath cells, macros etc...
				are contained in this tree.