/*----------------------------------------------------------------------*/
/* Copyright (C) 1994                                                   */
/*                                                                      */
/* Massachusetts Institute of Technology                                */
/* Concurrent VLSI Architecture Group                                   */
/* All rights reserved                                                  */
/*----------------------------------------------------------------------*/

/* File Name:	 	README				                */
/* Function:	        README file for /home/mm/rtl/lib/dlib           */
/*			 Common datapath cells           		*/
/*									*/
/* Language: 		Verilog						*/
/*									*/
/* Creator:		Steve Keckler  				        */
/* Creation date:	January 18, 1995  				*/
/* Last modified:	Whay Lee, June 18, 1995. added parity.v       	*/


This directory contains verilog models of commonly used datapath cells
(mostly muxes, latches, flip flops, plus some other common things).

address_adder.v - adder for addresses in IFU
dmux2r.v - 2 input radially encoded datapath mux (tri-state output)
dmux3r.v - 3 input radially encoded datapath mux (tri-state output)
dmux4r.v - 4 input radially encoded datapath mux (tri-state output)
dmux5r.v - 5 input radially encoded datapath mux (tri-state output)
dmux6r.v - 6 input radially encoded datapath mux (tri-state output)
dmux8r.v - 8 input radially encoded datapath mux (tri-state output)
dnltch1_1.v - negative transparent latch (1 input, 1 tri-state output)
dpdff1_1.v - positive edge triggered flip-flop (1 input, 1 tri-state output)
dpltch1_1.v - postive transparent latch (1 input, 1 inverted tri-state output)
nreg1_1.v - recirculating fwd trans neg latch (1 input, 1 tri-state output)
nreg2_1.v - recirculating fwd trans neg latch (2 inputs, 1 tri-state output)
nreg6_1.v - recirculating fwd trans neg latch (6 inputs, 1 tri-state output)
preg1_1.v - recirculating fwd trans pos latch (1 input, 1 tri-state output)
qreg1_1.v - recirc clk qual transparent latch (1 input, 1 tri-state output)
qreg1_2.v - recirc clk qual transparent latch (1 input, 2 tri-state outputs)
qreg2_1.v - recirc clk qual transparent latch (2 inputs, 1 tri-state output)
qreg2_1a.v - recirc clk qual transparent latch (2 input, 1 tri 1 norm output)
qreg2_2.v - recirc clk qual transparent latch (2 inputs, 2 tri-state outputs)
qreg3_1a.v - recirc clk qual transparent latch (3 input, 1 tri 1 norm output)
qreg4_1.v - recirc clk qual transparent latch (4 input, 1 tri output)
parity.v -  an even/odd parity generator.
