/*----------------------------------------------------------------------*/
/* Copyright (C) 1994                                                   */
/*                                                                      */
/* Massachusetts Institute of Technology                                */
/* Concurrent VLSI Architecture Group                                   */
/* All rights reserved                                                  */
/*----------------------------------------------------------------------*/

/* File Name:	 	README				                */
/* Function:	        README file for /home/mm/rtl/lib/stdlib         */
/*			 Macros built out standard cells		*/
/*									*/
/* Language: 		Verilog						*/
/*									*/
/* Creator:		Steve Keckler  				        */
/* Creation date:	January 18, 1995  				*/

This directory contains verilog models of the M-Machine standard cell
library.  Only those cells which are not directly synthesizable by
Synopsis are included here.  A complete list of the M-Machine standard
cells implemented in the Cadence library is at the bottom.

cka.v - clock-and driver:  for generating qualified clk
ncka.v - not-clock-and: for generating qualified ~clk
nltch.v - negative transparent latch
pdff.v - positive edge triggered flip flop
pltch.v - positive transparent latch (with inverted output)

-------------------------------------------------------------------------

In the Cadence standard cell library:

AND2: 2-input and gate
AND3: 3-input and gate
AND4: 4-input and gate

AOI21: and-or-invert (2-and or 1)
AOI22: and-or-invert (2-and or 2-and)
AOI31: and-or-invert (3-and or 1)
AOI32: and-or-invert (3-and or 2-and)
AOI33: and-or-invert (3-and or 3-and)
AOI211: and-or-invert (2-and or 1 or 1)
AOI221: and-or-invert (2-and or 2-and or 1)
AOI222: and-or-invert (2-and or 2-and or 2-and)
AOI2111: and-or-invert (2-and or 1 or 1 or 1)
AOI2211: and-or-invert (2-and or 2-and or 1 or 1)
AOI2221: and-or-invert (2-and or 2-and or 2-and or 1)
AOI2222: and-or-invert (2-and or 2-and or 2-and or 2-and)


CKA_1
CKA_2
CKA_4
CKA_8
NCKA_1
NCKA_2
NCKA_4
NCKA_8

INV_1
INV_2
INV_4
INV_8

NLTCH: negative level sensitive latch (with scan)
PLTCH: positive negative level sensitive latch (inverting, no scan)
PDFF:

NAND2: 2-input nand gate
NAND3: 3-input nand gate
NAND4: 4-input nand gate

NOR2: 2-input nor gate
NOR3: 3-input nor gate
NOR4: 4-input nor gate

OAI21: or-and-invert (2-or and 1)
OAI22: or-and-invert (2-or and 2-or)
OAI31: or-and-invert (3-or and 1)
OAI32: or-and-invert (3-or and 2-or)
OAI33: or-and-invert (3-or and 3-or)
OAI211: or-and-invert (2-or and 1 and 1)
OAI221: or-and-invert (2-or and 2-or and 1)
OAI222: or-and-invert (2-or and 2-or and 2-or)
OAI2111: or-and-invert (2-or and 1 and 1 and 1)
OAI2211: or-and-invert (2-or and 2-or and 1 and 1)
OAI2221: or-and-invert (2-or and 2-or and 2-or and 1)
OAI2222: or-and-invert (2-or and 2-or and 2-or and 2-or)

OR2: 2-input or gate
OR3: 3-input or gate
OR4: 4-input or gate

XOR2: 2-input exclusive-or gate
XNOR2: 2-input exclusive-or-invert gate




