Datapath pitch:
7168 lam = 112 lam per bit

Assume 800lam^2 per transistor for datapath layout (conservative)


FPU Multiply:

Booth encoder (radix 8):
  22 cells
    148 T per cell *  800l^2/T = 118Klam^2/cell
    cell height = 118Klam^2 / 112lam = 360lam 
    total area = 360 * 7168 = 2.5Mlam^2

64bit CPA Adder (3A):   9Mlam^2 (ballpark for pgk cells, 2 carry chains, output cells)

Multiply array:
    22 CSA
     30 transistors per CSA cell * 800l^2/T = 24Klam^2 
     cell height = 24K / 112 = 200lam 
     therefore total area = 22 * 200 * 7168 = 32Mlam^2

Mmux/invert for partial products 
    22 muxes: 
    total area = 70 lam high * 22 * 7168 = 11Mlam^2

Routing channels for CSA array 
    64 * 8lam high * 7168 = 2Mlam^2

half adder (64 bits) 
   10trans/cell * 800lam^trans = 8Klam^2 
   cell height = 8K/112 = 70lam 
   total area = 70*7168 = 0.5Mlam^2

128 bit CPA:  18Mlam^2

64 bit or tree (sticky bits) assume 10lam high 
  total area = 0.07Mlam^2

pipeline latches (8) 
   assume 70lam high 
   total area = 8 * 70 * 7168 = 5Mlam^2

total = 80Mlam^2

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FPU Add:

64 bit alignment shifter  = 64 * 8lam high * 7168 = 2Mlam^2
64 bit CPA = 9Mlam^2
LZ detector = 6Mlam^2
64 bit normalization shifter = 64 * 8lam high * 7168 = 2Mlam^2
64 bit CPA (round) = 9Mlam^2

total = 28Mlam^2

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overall total = 108Mlam^2
with 20% control overhead = 130Mlam^2



