Implement mantissa arithmetic in 2's complement and extend bits when
necessary for negative numbers.  For FP mantissas (only ~50 bits) we
do unsigned multiply and zero out top bits.  (array ends up being 128
bits wide).

Adder
  - Carry propagate: 64bit, same as intu

Multiplier
  - What radix booth encoding (radix-8)
        - with radix-4 we get 32 partial products
        - with radix-8 we get 22 partial products

  - What type of CSA (3-2, 7-3)

  3,2 counter - add 2 bits per 

FMulA
  - Can this in fact be done without additional delay 
    (one more add step (CSA) at bottom of multiply)

Divider
  - SRT - what radix
    	- what clock rate
    	- latches at input and output to "double cyle" it

FMOV, ITOF, FTOI
  - tap into the appropriate place in to re-use logic and reserve
    a spot in the pipeline for use of CSW (control scoreboard)

CSW and reg-port access
  - When FDIV op completes, it automatically wins arbitration for
other resources.  MUL/ADD unit is stalled if it has something that
cycle just as if it had lost CSW arbitration.
    

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