From omv@ai.mit.edu Fri Jul 21 11:50:49 1995
Return-Path: <omv@ai.mit.edu>
From: omv@ai.mit.edu (Dan Hartman)
Date: Thu, 20 Jul 95 13:33:16 EDT
To: skeckler
Subject:  rounding scheme


Original Pipeline:	Effective
			Calcuation	Rnd=0		Rnd=1
			------------------------------------------
  ab  c			Same Sign (add)	ab+c		ab+c+1
  |   |				
  |  +-+		Opposite Signs	ab+c+1		ab+c+2
  |  |X| (xor)		(pos result)
  |  +-+	
  |   |			Opposite Signs	~(ab+c+1)	~(ab+c+1)+1
+-------+		(neg result)			~(ab+c)
| add   |- sub		(no +1 on L bit)
+-------+	
    |			Opposite Signs	~(ab+c+1)+1	~(ab+c+1)+2
+-------+		(neg result)	~(ab+c)		~(ab+c-1)
|lz&shft|		(+1 on L bit)
+-------+	
    |			
+-------+	
| add   |- rnd	
+-------+	
    |			

The original pipeline functions by possibly inverting the c input for
different signed ab & c, then adding them together, along with +1 if
the c input has been inverted.  This result is then shifted and
rounded.  Hence, 6 possible outputs are possible: ab+c, ab+c+1,
ab+c+2, ~(ab+c-1), ~(ab+c), and ~(ab+c+1).  Not counting inversion,
this gives 4 cases, ab+c-1, ab+c, ab+c+1, and ab+c+2.  All of these
cases can be computed by two simultaneous adds (ab+c-1) + 0/1 and
(ab+c+1) + 0/1.



New Pipeline:		
			
			
  ab  c				
  |   |				
 +-+ +-+			
 |X| |X| (xor)			
 +-+ +-+			
  |   |				
  |   +---------------+		
  +---|-----------+   |		
  |   |		  |   |		
+-------+	+-------+	
|CSA add|- (+1)	|CSA add|- (-1)	
+-------+	+-------+	
  |   |		  |   |		
+-------+	+-------+	
|add 0/1|	|add 0/1|	
+-------+	+-------+	
  |   |           |   |
+-----------------------+
|      selector mux     |
+-----------------------+
    |
+-------+			
|lz&shft|			
+-------+			
    |				

One slight of hand that has been done here is that we assume that the
inversion and +1 always results in a +1 on the high bits that we are
computing in parallel.  Obviously, this does not have to be the case
if the low bits of the c input are not 0.  Therefore, rather than
inverting C always, one can invert the input (ab or c) that is not
shifted - this is guaranteed to give an overflow on the low bits, and
only requires a small change in the control circuitry for the correct
sign at the output.

What remains is to decide which number to add to the low order bits.
This will depend on how far the answer from the add needs to be
shifted.  Therefore, two selections will be done on the add - one that
assumes a 0 input on the round and one that assumes a 1 input.  Based
on the output of the 0 input select, the shifting amount will be
decided: 1 right (overflow), no shift, 1 left, more than 1 left.  This
can be decided by looking at the high 4 bits of the sum.



Then, a number from the following table will be added to the sum of
the low 3 bits of each operand.

Shift Mode	Number to be added
>=2 left	0001
1 left		0010
no shift	0100
overflow	1000

When this four bit quanity is added to the three low bits, the fourth
bit will be checked, and its value will select which value to output.

Rounding to even will take place as usual, though only occuring when
no shift or overflow occurs (will affect either L0 or L1 bit
respectively).  Since this will not affect the value of the LZ detect,
its time is not critical.


From omv@ai.mit.edu Wed Jun  5 10:40:35 1996
Return-Path: <omv@ai.mit.edu>
From: omv@ai.mit.edu (Dan Hartman)
Date: Tue, 26 Sep 1995 12:38:47 -0400
To: skeckler
Subject: First half, control stuff:


********* Multiplier Rounding Control *********

OUTPUTS
-------

MCin, MSin		2 bits
	- outputs from multiplier output
	- driven directly from p-latches (Stage 2, 3)
	- used to determine rounding - Rc and Rs bit respectively

lowsticky		1 bit
	- output from multiplier output
	- driven from combination logic after p-latch (Stage 2, 3)
	- used to determine rounding - S bit

lowcarry		1 bit
	- output from multiplier output
	- driven from combination logic after p-latch (Stage 2, 3)
	- used to determine rounding - carry from low word adder

high53			1 bit
	- output from multiplier output
	- driven from combination logic after p-latch (Stage 2, 3)
	- used to shift right by 1 in overflow case

high0			1 bit
	- output from multiplier output
	- driven from combination logic after p-latch (Stage 2, 3)
	- used to determine rounding - L bit

low63			1 bit
	- output from multiplier output
	- driven from combination logic after p-latch (Stage 2, 3)
	- used to determine rounding - R bit (without rounding added)

PreOvr			1 bit
	- output from multiplier output
	- driven from combination logic after p-latch (Stage 2, 3)
	- used to determine rounding - Ovr bit

INPUTS
------

SelRnd0, SelRnd1	2 bits
	- input to multipler rounding logic - controls a*b/a*b+1 selection
	- drives to combinational logic that feeds an N latch. (Stage 2,3)
	- If integer mult, SelRnd1 = (Rs & Rc) | (Rs & lowcarry)
					| (Rc & lowcarry)
	- If floating mult, SelRnd1 = (lowcarry | ~RsRc) & (PreOvr | low63)
	- otherwise, value is unimportant
	- SelRnd0 = ~SelRnd1

Overflow, Overflow_L	2 bits
	- input to multipler rounding logic - controls shift-right
	- drives to combinational logic that feeds an N latch. (Stage 2,3)
	- if floating mult, Overflow = high53.  Otherwise, =0
	- Overflow_L = ~Overflow

RsRc, RsRc_L		2 bits
	- input to multipler rounding logic - adds in extra rounding bit
	- drives to combinational logic that feeds an N latch. (Stage 2,3)
	- if floating mult, RsRc = Rs | Rc.  Otherwise, =0
	- RsRc_L = ~RsRc

L0Force, L0Force_L	2 bits
	- input to multipler rounding logic - force L0 bit for round-to-even
	- drives to combinational logic that feeds an N latch. (Stage 2,3)
	- if floating mult, L0Force = ((~high53) & low63 & Sticky) |
	  (high53 & ~high0 & (~low63) & Sticky),
	- L0Force_L = ~L0_Force

FMUL, IMUL, HMUL, MULbyp, FMUL_L, IMUL_L, HMUL_L, MULbyp_L 	8 bits
	- input to selection mux after rounding logic
	- drives to combinational logic that feeds an N latch. (Stage 2,3)
	- if FMUL, FMULA, FMUL = 1, if HMUL, HMUL = 1, if IMUL, IMUL = 1,
	  otherwise MulByp = 1
	- FMUL_L = ~FMUL, HMUL_L = ~HMUL, IMUL_L = ~IMUL, MULByp_L = ~MULByp



From omv@ai.mit.edu Wed Jun  5 10:41:41 1996
Return-Path: <omv@ai.mit.edu>
From: omv@ai.mit.edu (Dan Hartman)
Date: Tue, 26 Sep 1995 18:14:45 -0400
To: skeckler@ai.mit.edu
In-Reply-To: <199509262213.SAA09968@kiwi.ai.mit.edu> (skeckler@ai.mit.edu)
Subject: Re: rest of signals


********* Multiplier Rounding Control *********

OUTPUTS
-------

MCin, MSin		2 bits
	- outputs from multiplier output
	- driven directly from p-latches (Stage 2, 3)
	- used to determine rounding - Rc and Rs bit respectively

lowsticky		1 bit
	- output from multiplier output
	- driven from combination logic after p-latch (Stage 2, 3)
	- used to determine rounding - S bit

lowcarry		1 bit
	- output from multiplier output
	- driven from combination logic after p-latch (Stage 2, 3)
	- used to determine rounding - carry from low word adder

high53			1 bit
	- output from multiplier output
	- driven from combination logic after p-latch (Stage 2, 3)
	- used to shift right by 1 in overflow case

high0			1 bit
	- output from multiplier output
	- driven from combination logic after p-latch (Stage 2, 3)
	- used to determine rounding - L bit

low63			1 bit
	- output from multiplier output
	- driven from combination logic after p-latch (Stage 2, 3)
	- used to determine rounding - R bit (without rounding added)

PreOvr			1 bit
	- output from multiplier output
	- driven from combination logic after p-latch (Stage 2, 3)
	- used to determine rounding - Ovr bit

INPUTS
------

SelRnd0, SelRnd1	2 bits
	- input to multipler rounding logic - controls a*b/a*b+1 selection
	- drives to combinational logic that feeds an N latch. (Stage 2,3)
	- If integer mult, SelRnd1 = (Rs & Rc) | (Rs & lowcarry)
					| (Rc & lowcarry)
	- If floating mult, SelRnd1 = (lowcarry | ~RsRc) & (PreOvr | low63)
	- otherwise, value is unimportant
	- SelRnd0 = ~SelRnd1

Overflow, Overflow_L	2 bits
	- input to multipler rounding logic - controls shift-right
	- drives to combinational logic that feeds an N latch. (Stage 2,3)
	- if floating mult, Overflow = high53.  Otherwise, =0
	- Overflow_L = ~Overflow

RsRc, RsRc_L		2 bits
	- input to multipler rounding logic - adds in extra rounding bit
	- drives to combinational logic that feeds an N latch. (Stage 2,3)
	- if floating mult, RsRc = Rs | Rc.  Otherwise, =0
	- RsRc_L = ~RsRc

L0Force, L0Force_L	2 bits
	- input to multipler rounding logic - force L0 bit for round-to-even
	- drives to combinational logic that feeds an N latch. (Stage 2,3)
	- if floating mult, L0Force = ((~high53) & low63 & Sticky) |
	  (high53 & ~high0 & (~low63) & Sticky),
	- L0Force_L = ~L0_Force

FMUL, IMUL, HMUL, MULbyp, FMUL_L, IMUL_L, HMUL_L, MULbyp_L 	8 bits
	- input to selection mux after rounding logic
	- drives to combinational logic that feeds an N latch. (Stage 2,3)
	- if FMUL, FMULA, FMUL = 1, if HMUL, HMUL = 1, if IMUL, IMUL = 1,
	  otherwise MulByp = 1
	- FMUL_L = ~FMUL, HMUL_L = ~HMUL, IMUL_L = ~IMUL, MULByp_L = ~MULByp



********* Alignment stage control *********

OUTPUTS
-------

shfted<2:0>	3 bits
	- output from alignment shifter - R, G, and S bits of shifted result
	- driven by N-latch (Stage 4, 5)
	- used to determine adder rounding

INPUTS
------

alnBT_v0, alnNB_v0, alnQW_v0	12 bits
	- input to alignment stage specifying how far shift should go
	- drives combination logic that gets latched by a p latch
	- set to amount to shift argument - one hot encoding for each
	  set of 4 bits (IE, alnBT0 specifies no shift, alnBT1 specifies
	  1 bit shift, etc)

subtract, subtract_L		2 bits
	- input to alignment stage specifying if non-shfted number should be
	  inverted
	- drives combination logic that feeds a p latch
	- should be set if FADD (or FPMULA) & opposite signs, or FSUB
	  and same signs
	- subtract_L = ~subtract


********* Adder Rounding stage control *********

OUTPUTS
-------

nrnd<0>				1 bit
	- output from rounding stage specifying what L bit is equal to
	- comes from combinational logic after n latch
	- used to do round-to-nearest-even

det<3:0>			4 bits
	- output from rounding stage specifying which shift mode
	- comes from combinational logic after n latch
	- used to determine which number to add to LSB's.

neg_res				1 bit
	- output from rounding stage specifying whether result was negative
	- comes from combinational logic after n latch
	- used to correctly determine rounding

INPUTS
------

sub_del, sub_del_L		2 bits
	- input to add rounding stage specifying if correct factor of 1
	  should be added for subtracts.
	- drives combinational logic that feeds a p latch
	- should be set if FADD (or FPMULA) & opposite signs, or FSUB
	  and same signs
	- sub_del_L = ~sub_del
	- delayed version of above by 1 clock cycle.

ADD_Byp, ADD_AByp_L		2 bits
	- input to bypass mux in add rounting logic
	- drives combinational logic that feeds a p latch
	- ADD_Byp = 1 for fadds/fsubs/fpmula, 0 for multiplies
	- ADD_Byp_L = ~ADD_Byp
	
negFTOI, negFTOI_L		2 bits
	- input to add rounding logic to force negative avalue
	- drives combinational logic that feeds a p latch
	- negFTOI = 1 for FTOI command when floating point input is
	  negative, 0 otherwise
	- negFTOI_L = ~negFTOI

Arnd, Arnd_L			2 bits
	- input to select between A+C and A+C+1 in add rounding logic
	- drives combinational logic that feeds a p latch
	- Arnd = bit 3 of  (shfted[2:0] ^ 3{neg_res}) + neg_res + det[3:0]
	- Arnd_L = ~Arnd

AForceL0, AForceL0_L, AForceL1, AForceL1_L	4 bits
	- input to rounding logic to force L1 or L0 bit low
	- drives combinational logic that feeds a p latch
	- AForceL1 = ~det[3] & nrnd0 & ~new[2] & ~new[1] & ~new[0]
	  where new[2:0] is the result of the add for determing rounding
	- AForceL0 = ~det[2] & ~new[2] & ~new[1] & ~new[0]
	- AForceL1_L = ~AForceL1;
	- AForceL0_L = ~AForceL0;

********* Adder Rounding stage control *********

OUTPUTS
-------

NLZs				6 bits
	- output from normalization logic - number of leading zeros
	- arrives from combinational logic after a p-latch
	- used for postnormalization

zero				1 bit
	- output from normalization logic - is result zero?
	- arrives from combinational logic after a p-latch
	- used for postnormalization

INPUTS
------

Aoverflow, Aoverflow_L		2 bits
	- input to normalization stage - specifies right shift by 1 bit
	- drives combational logic before n latch
	- Aoverflow = det[3]
	- Aoverflow_L = ~Aoverflow

NormBT, NormNB, NormQW		12 bits
	- input to normalization stage - specifies left normalization shift
	- drives combational logic before n latch
	- one hot encoding of how much to left shift - more or less just
	  a simple encoding of NLZs, with a maximum for gradual underflow

lobits				2 bits
	- input to normalization stage - low two bits for shifter
	- drives combational logic before n latch
	- low 2 bits - R & G bits - for shifting in in case of normalization
	



From omv@ai.mit.edu Wed Jun  5 10:43:58 1996
Return-Path: <omv@ai.mit.edu>
From: omv@ai.mit.edu (Dan Hartman)
Date: Wed, 27 Sep 1995 15:49:19 -0400
To: skeckler
Subject: Rounding Logic


There are two seperate issues.  The first is to correctly add together
the two numbers, and two's complement the result if it is negative.
The second is to perform the actual rounding.

To add the numbers correctly, one must correctly chose between AB+C,
AB+C+1, and AB+C+2.  The following table shows the correct answers for
each possible case

Operation	Resultant Sign		Result		Result + 1
Add		Positive		AB+C		AB+C+1
Subtract	Positive		AB+C+1		AB+C+2
Subtract	Negative		~(AB+C+1)	~(AB+C)

Hence, we can chose the correct two possible answers given the
operation and the resultant sign (with a possible inversion
necessary).  What remains is simple to choose between the rounded and
non rounded results.

Basically, the rounding strategy resolves around the fact that there are
only 4 different places to round, based on how much normalization must
occur.

This is based on where the R bit will actually be.  Shifts greater
than 1 are all equilivant due to the sticky bit being extended for
the normalizing shift.

			Rounding Location
Overflow		L bit
No shift		R bit
Shift by 1		G bit
Shift by 2 or more	S bit

So, by adding in the rounding bit to the low order bits before the
normalize, the correct answer will result.  Since the R, G, and S bits
are all sent to the control logic, the control simply needs to send
back a signal saying whether AB+C or AB+C+1 should be selected.



