From omv@ai.mit.edu Wed Jun  5 10:31:48 1996
Return-Path: <omv@ai.mit.edu>
From: omv@ai.mit.edu (Dan Hartman)
Date: Thu, 14 Sep 1995 23:38:40 -0400
To: skeckler
Subject: Signal Chart


FPMULA example:

Outputs from Datapath
Asrt	=	Asserted
Stbl	=	Stable

		Phase
		0	1	2	3	4	5	6	7
MCin				Asrt	Stbl
MSin				Asrt	Stbl
lowsticky			Asrt	Asrt
lowcarry			Asrt	Asrt
high53				Asrt	Asrt
high0				Asrt	Asrt
low63				Asrt	Asrt
PreOvr				Asrt	Asrt

RGS						Asrt	Stbl

nrnd<0>							Asrt	Asrt
det<3:0>						Asrt	Asrt
neg_res							Asrt	Asrt

NLZs								Asrt	Asrt
zero								Asrt	Asrt


Inputs to Datapath

SelRnd0				sr	sr
SelRnd1				sr	sr
Overflow			Ovr	Ovr
Overflow_L			Ovr	Ovr
RsRc				rsrc	rsrc
RsRc_L				rsrc	rsrc	
L0Force				l0f	l0f
L0Force_L			l0f	l0f

FMUL_v1					1
IMUL_v1					0
HMUL_v1					0
MULbyp_v1				0

alnBT_v0					aln
alnNB_v0					aln
alnQW_v0					aln
subtract_v0					sub
subtract_L_v0					sub
preshft2_v0					0
preshft2_L_v0					1
ShftAB_v0					shftabc
ShftC_v0					shftabc

Arnd_v0								arnd
Arnd_L_v0							arnd
negFTOI_v0						0	0
negFTOI_l_v0						1	1
sub_del_v0						sub	sub
sub_del_v0						sub	sub
AByp_v0								0
AByp_L_v0							1
AForceL1							afl1
AForceL1_L							afl1
AForceL0							afl0
AForceL0_L							afl0

Aoverflow_v1								aovr
Aoverflow_L_v1								aovr
NormBT_v1								norm
NormNB_v1								norm
NormQW_v1								norm
lobits									lobits

IMUL_Bypass								0
IMUL_Bypass_L								1

Cdrop1		0	0	
Cdrop1		1	1
Cdrop2				0	0
Cdrop2				1	1
Cdrop3						0	0
Cdrop3						1	1

sr =>	SelRnd0 = (lowcarry | ~RsRc) & (PreOvr | low63)
	SelRnd1 = ~SelRnd0

ovr =>	Overflow = high53;

rsrc =>	RsRc = MCin | MSin

l0f =>	L0Force = ((~high53) & low63 & lowsticky) | (high53 & high0 &
			(~low63) & lowsticky);

aln =>	Feed in amount that ab and c exponenets differ - one hot
	encoding where the MSB control means shift by 3 and the LSB means
	don't shift

sub =>	Assert if signs differ between ab and c

shftabc => Assert ShftAB is C has the higher exponenet, otherwise
	assert ShftC

arnd =>	See Addition Rounding Logic
afl1 =>	See Addition Rounding Logic
afl0 =>	See Addition Rounding Logic

lobits => See Addition Rounding Logic
aovr =>	Assrted if addition result overflows (d[3])
norm =>	One hot encoding for normlize shifters


