IDIV

a_sgn
a_uflw_L
b_sgn
b_uflw_L

		      ITER
divide		1	1	1	1	1	1	1
sqrt		0	0	0	0	0	0	0
	
start		1	0	0	0	0	0	0
eval		0	1	0	0	0	0	0

qp2		0	x	0	0	0	0	0
qp1		0	x	0	0	0	0	0
q0		0	x	0	0	0	0	0
qn1		0	x	0	0	0	0	0
qn2		0	x	0	0	0	0	0

LZDETECT
  b_lz 		1	0	0	0	0	0	0
  dbus_lz	0	0	0	1	0	0	0
  rems_lz	0	0	0	0	1	0	0
  zero_lz	0	1	1	0	0	1	1

ADDER
  carryin	-	-	0	-	0	-	-
  invert	-	-	0	-	0	-	-

  zero_a	1	1	0	1	0	1	1
  dbus_a	0	0	0	0	1	0	0
  rems_a	0	0	1	0	0	0	0
  b_a		0	0	0	0	0	0	0

  zero_b	1	1	0	1	0	1	1
  stky_b 	0	0	0	0	1	0	0
  remc_b	0	0	1	0	0	0	0

  cpa_lbus1	0	0	1	0	1	0	0

SHIFTER	
  shiftBT[6:0]	A	-	-	B	-	-	-
  shiftNB[6:0]	A	-	-	B	-	-	-
  shiftQW[6:0]	A	-	-	B	-	-	-
  lext		0	-	-	0	-	-	-
  hext		-	-	-	r_sgn	-	-	-
	
  b_sh		1	0	0	0	0	0	0
  rems_sh	0	0	0	0	0	0	0
  dbus_sh	0	0	0	1	0	0	0
  zero_sh	0	1	1	0	1	1	1
	
  sh_lbus2	1	0	0	1	0	0	0
  to_rems_int	0	1	1	0	1	1	1
  to_rems_sqevn 0	0	0	0	0	0	0
  to_rems_sqodd	0	0	0	0	0	0	0
  to_reml	0	0	0	0	0	0	0
  to_div	1	0	0	1	0	0	0

DIV
  hold_div	0	1	1	0	1	1	1
  lbus2_div	1	0	0	1	0	0	0
  lbus1_div	0	0	0	0	0	0	0
		
  div_dbus	1	1	1	0	1	1	1

REMC
  zero_remc	1	0	1	1	1	1	1
  lbus2_remc	0	1	0	0	0	0	0

RES
  r_sgn		-	-	-	-	-	x	-
  r_exp[10:0]	-	-	-	-	-	x	-
  errtype[9:0]	-	-	-	-	-	x	-
	
  final_res	0	0	0	0	0	x	0
  int		-	-	-	-	-	0	-
  flt_norm	-	-	-	-	-	x	-
  flt_plus1	-	-	-	-	-	x	-
  flt_ovr	-	-	-	-	-	x	-
	
  a_res		x	0	0	0	0	0	0
  b_res		x	0	0	0	0	0	0
  ip_res	x	0	0	0	0	0	0
  hold_res	0	1	1	1	1	0	1
  errval_res	0	0	0	0	0	x	0

  res_wb	0	0	0	0	0	0	1

QREG
  q0_hold	0	q0	1	1	1	1	1
  		
  qp_dbus	0	0	0	x	0	0	0
  qn_dbus	0	0	0	x	0	0	0

REMS
  inta_rems	0	0	0	0	0	0	0
  flta_rems	1	0	0	0	0	0	0
  lbus1_rems	0	0	1	0	1	0	0
  lbus2_rems	0	0	0	0	0	0	0
  hold_rems	0	0	0	1	0	1	1

  zero_reml	1	0	1	1	1	1	1
  shift_reml	0	1	0	0	0	0	0
  lbus2_reml	0	0	0	0	0	0	0
