*** Signal names and descriptions for the dsq unit ***

Note: datapath requires complementary inputs in several cases; only
one sense of the signal is listed here

*** INPUTS ***

a[63:0]
b[63:0] 
ip[63:0]

clk
clk_L

a_sgn		sign of a
a_uflw_L	underflow for a
b_sgn		sign of b
b_uflw_L	underflow for b

					      
divide		operation
sqrt		

start		asserted before iterative stage
eval[_L]	asserted during iterative stage

qp2		quotient/root bit for current iteration
qp1		
q0		
qn1		
qn2		

LZDETECT
  b_lz[_L] 	zero detect of b
  dbus_lz[_L]	zero detect of dbus
  rems_lz[_L]	zero detect of rems
  zero_lz[_L]	no zero detect (ground input)

ADDER
  carryin	carryin for adder
  invert[_L]	invert augend

  zero_a[_L]	augend is zero
  dbus_a[_L]	augend is dbus
  rems_a[_L]	augend is rems
  b_a[_L]		augend is b

  zero_b[_L]	addend is zero
  stky_b[_L]	addend is {58'b0,1'b1,9'b0}
  remc_b[_L]	addend is remc

  cpa_lbus1	drive lbus1 with adder output

SHIFTER
  shiftBT[6:0]	shift magnitude
  shiftNB[6:0]	
  shiftQW[6:0]	
  lext[_L]		low-bit replacement for left-shifts
  hext[_L]		high-bit replacement for right-shifts

  b_sh[_L]	Shift b
  rems_sh[_L]	Shift rems
  dbus_sh[_L]	Shift dbus
  zero_sh[_L]	No shift (ground input)

  sh_lbus2	drive lbus2 with shifter output
  to_rems_int	result to rems register	(for idiv
  to_rems_sqevn	result to rems register (for fsqrt, even exponent)
  to_rems_sqodd result to rems register (for fsqrt, odd exponent)
  to_reml	result to reml register
  to_div	result to div register

DIV
  hold_div[_L]	keep current value of div
  lbus2_div[_L]	load div with lbus2 
  lbus1_div[_L]	load div with lbus1 
	
  div_dbus	drive dbus with div

REMC
  zero_remc	load remc with zero
  lbus2_remc	load remc with lbus2 

RES
  r_sgn		sign of result
  r_exp[10:0]	exponent of result
  errtype[9:0]	type of error (when result is errval)

  final_res	write result to res register (not errval)
  int[_L]	for integer divide
  flt_norm[_L]	for flt rounding, no add necessary
  flt_plus1[_L]	for flt rounding, add 1 at sticky bit position
  flt_ovr[_L]	for flt rounding, overflow
	
  a_res		load res with a
  b_res		load res with b
  ip_res	load res with ip
  hold_res	keep current value of res
  errval_res	write errval to res
 
  res_wb	drive wb with res


QREG
  q0_hold	same as q0 during iterative stage; asserted to 
  		hold value of qn/qp after iterative stage
  qp_dbus	drive dbus with qp
  qn_dbus	drive dbus with qn

REMS
  inta_rems	load rems with integer a
  flta_rems	load rems with floating point a
  lbus1_rems	load rems with lbus1
  lbus2_rems	load rems with lbus2
  hold_rems	keep current value of rems

  zero_reml[_L]	load rem_low with zero
  shift_reml[_L]shift rem_low left by two bits
  lbus2_reml[_L]load rem_low with lbus2


*** OUTPUTS ***

a[63:52]	sign and exponent for a
b[63:52]	sign and exponent for b

zero		asserted if lzdetect input is zero
lz_pos[5:0]	position of first high bit in lzdetect input

div[63:60]	most significant bits of divisor (for divide iterative stage)
		and normalized quotient (for round overflow determination)
div[9:0]	least significant bits of normalized quotient (for 
		sticky bit determination)

qp[64:60]	most significant bits of root (for sqrt iterative stage)

rem_pred[7:0]	predicted bits of remainder (for iterative stage)

top_rem_s[3:0]	top bits of remainder (for remainder sign and zero-detect)

wb[63:0]	writeback for final result