********************************************************************************

Need DP ECO - NLatch before tristate to get fast feed-through

*** IDIV ***

Currently sitting at 46 half cycles.
Opporunity for reduction:
    - Compress 0,1    			ECO
    - Compress 17,18			ECO
Best case (with 2 cycle add): 44

Best case (with 1 cycle add): invert B/Rem_c/Q_P -> 41
********************************************************************************

INIT = 0
1.  Load A into rem_s (unsigned)
2.  Load B into div (sign extended)
3.  Grab a/b/ip in res register for errval usage

INIT = 1
4.  Invert B if negative

INIT = 2
5.  Invert B if negative, result in div

INIT = 3
6. LZ detect on B

INIT = 4
7. Shift A up (K bits) to generate a_lo, store in reml

INIT = 5
8. Shift A down up to generate a_hi, store in rem_s
   to match magnitude to normalize B
9. Shift reml up 2 bits

INIT = 6
10. Shift B (div) up K bits
11. Shift reml up 2 bits


ITER = 1->33
12.  Iterative stage


FINAL = 0,1
13.  Add rem_c and rem_s, store back in rem_s (remainder)

FINAL = 2
14.  LZ detect on rem_s to find if result is exact

FINAL = 3
15. Add quotient (q_p/q_n) with invert/carry in for inversion if necessary

FINAL = 4
16. Add quotient (q_p/q_n) with invert/carry in for inversion if necessary
17. Select adder result or errval

FINAL = 5
18.  Drive result to WB




********************************************************************************

*** FDIV ***

Currently sitting at 40 half cycles.
Opporunity for reduction:
    - 28 iterations (maybe)
    - Compress 16,17 into 1 (requires latching element)	ECO
    - Swap 10 and 12, move 13 into (5) 
    - Compress 15,16 into 1                             ECO
Best case (with 2 cycle add): 36 half cycles
Best case (with 1 cycle add): 34 half cycles
********************************************************************************

INIT = 0
1.  Load A into rems w/ correct bit for Underflow
2.  Load B into div w/ correct bit for Underflow
3.  LZ detect on B (with UF bit)
4.  Grab a/b/ip in res register for errval usage

INIT = 1
5.  LZ detect on A (in rem_s)
6.  Shift B up based on LZ detect and store back in div


ITER = 1->29
7.  Iterative stage


FINAL = 0,1
8.  Add rem_c and rem_s, store back in rem_s (remainder)

FINAL = 2
9.  LZ detect on quotient (q_p/q_n) based on sign of remainder

FINAL = 3
10.  Shift quotient (q_p/q_n) up to generate sticky bits (slo_sticky)
    store result in rem_s
11.  LZ detect on remainder (zero detect) for more sticky info

FINAL = 4
12.  Shift quotient (q_p/q_n) down into position for underflow 
    (if necessary), store result in div
13.  LZ detect (zero detect) on slo_sticky for rounding

FINAL = 5
14.  Generate div + 1 (in LSB position) for rounding and store in rem_s

FINAL = 6
15.  Generate div + 1 (in LSB position) for rounding and store in rem_s

FINAL = 7
16.  Select div, div+1 as well as NAN, errval

FINAL = 8
17.  Drive result to WB


********************************************************************************

*** FSQRT ***

Currently sitting at 40 half cycles.
Opporunity for reduction:
    - 28 iterations: 2
    - Remove INIT = 2
    - Compress 11,12		ECO
    - Compress 10,11            ECO
Best case (with 2 cycle add): 35 half cycles
Best case (with 1 cycle add): 33 half cycles
********************************************************************************

INIT = 0
1.  Load B into div w/ correct bit for Underflow
2.  LZ detect on B (with UF bit)
3.  Grab b/ip in res register for errval usage

INIT = 1
4.  Shift B up based on LZ detect and even/odd and store in rems

INIT = 2
5.


ITER = 1->30
6.  Iterative stage


FINAL = 0,1
7.  Add rem_c and rem_s, store back in rem_s (remainder)

FINAL = 2
8.  Shift quotient (q_p/q_n) down 1 bit position, store result in div

FINAL = 3
9.  Generate div + 1 (in LSB position) for rounding and store in rem_s

FINAL = 4
10.  Generate div + 1 (in LSB position) for rounding and store in rem_s

FINAL = 5
11.  Select div, div+1 as well as NAN, errval

FINAL = 6
12.  Drive result to WB
