From jbowers@ai.mit.edu Thu Aug 24 14:31:29 1995
Return-Path: <jbowers@ai.mit.edu>
From: jbowers@ai.mit.edu (Jeff Bowers)
Date: Fri, 18 Aug 95 15:20:59 EDT
To: skeckler
Subject:  dsq unit signals


*** Signal names and descriptions for the DSQ unit ***

DATAPATH

a[63:0]			Global buses
b[63:0]
c[63:0]
ip[63:0]
wb[63:0]
cswitch1[63:0]
cswitch2[63:0]
mswitch1[63:0]
mswitch2[63:0]

rem_s[67:0]		Output of rem_s register
next_rem_s_L[67:0]	Writeback bus for rem_s register

rem_c[67:0]		Output of rem_c register
next_rem_c_L[67:0]	Writeback bus for rem_c register

div[67:0]		Output of div register
next_div_L[67:0]	Writeback bus for div register

next_rem_low_L[67:0]	Writeback for rem_low register

qp[67:0]		Output of Q register		
qn[67:0]		Output of Q-1 register

sel[33:0]		Iteration index ("K")

a_div[67:0]		div (if divide) or qp (if sqrt)
b_div[67:0]		div (if divide) or qn (if sqrt)


CONTROL

clk			Duh
clk_L

sqrt 			Mode select
divide

start			Start iterative stage
eval			Perform iteration

qp2			One-hot quotient bit select (iterative stage)
qp1
q0
qn1
qn2

rem_pred[7:0] (output)	Predicted remainder for next iter stage

inta_rems		Write "a" (integer) to rems register
flta_rems		Write "a" (floating point) to rems register

rnd_norm		Write result to wb (do not round up)
rnd_add1		Write result to wb (round up)
rnd_ovrflow		Write result to wb (rounding overflow)

a_uflw_L		Underflow for a
b_uflw_L		Underflow for b

a_sgn			Sign of a
b_sgn			Sign of b

shifter:
    shiftQW[6:0]	One-hot shift magnitude 
    shiftNB[6:0]
    shiftBT[6:0]
    lext		Low bit extension (for left shift)
    lext_L
    hext		High bit extension (for right shift)
    hext_L
    
    rems1_sh		Shift rems
    rems2_sh
    div_sh		Shift div
    q_sh		Shift Q (qp)
    q_1_sh		Shift Q_1 (qn)	
    b_sh		Shift b

    sh_remc		Write shift output to remc register
    sh_rems		"                   " rems register
    sh_reml		"                   " rem_low register
    sh_div		"                   " div register

    remsft_0		Mux select for 66-bit remainder shift
    remsft_1		    (writeback to wb)
    remsft_2

adder:
    carryin		
    invert		Invert augend
    invert_L
    
    b_a			Augend is b
    rems_a		Augend is rems
    remc_a		Augend is remc
    q_a			Augend is Q (qp)
    q_1_a		Augend is Q_1 (qn)
    div_a		Augend is div

    rems_b		Addend is rems
    rems_b_L		
    zero_b		Addend is 68'b0
    zero_b_L
    stky_b		Addend is {58'b0,1'b1,9'b0}
    stky_b_L
    remc_b		Addend is remc
    remc_b_L

    cpa_wb		Write sum to wb
    cpa_rems		Write sum to rems register
    cpa_div		Write sum to div register

lzdetect:
    div_lz		Zero detect of div
    rems_lz		Zero detect of rems
    b_lz		Zero detect of b
    q_lz		Zero detect of Q (qp)
    q_1_lz		Zero detect of Q_1 (qn)

    zero (output)	Is the input zero?
    hbits[2:0] (output)	Byte position of leading zero
    lbits[2:0] (output)	Bit position of leading zero



