From omv@ai.mit.edu Thu Sep 28 18:23:17 1995
Return-Path: <omv@ai.mit.edu>
From: omv@ai.mit.edu (Dan Hartman)
Date: Tue, 26 Sep 1995 18:14:45 -0400
To: skeckler@ai.mit.edu
In-Reply-To: <199509262213.SAA09968@kiwi.ai.mit.edu> (skeckler@ai.mit.edu)
Subject: Re: rest of signals


********* Multiplier Rounding Control *********

OUTPUTS
-------

MCin, MSin		2 bits
	- outputs from multiplier output
	- driven directly from p-latches (Stage 2, 3)
	- used to determine rounding - Rc and Rs bit respectively

lowsticky		1 bit
	- output from multiplier output
	- driven from combination logic after p-latch (Stage 2, 3)
	- used to determine rounding - S bit

lowcarry		1 bit
	- output from multiplier output
	- driven from combination logic after p-latch (Stage 2, 3)
	- used to determine rounding - carry from low word adder

high53			1 bit
	- output from multiplier output
	- driven from combination logic after p-latch (Stage 2, 3)
	- used to shift right by 1 in overflow case

high0			1 bit
	- output from multiplier output
	- driven from combination logic after p-latch (Stage 2, 3)
	- used to determine rounding - L bit

low63			1 bit
	- output from multiplier output
	- driven from combination logic after p-latch (Stage 2, 3)
	- used to determine rounding - R bit (without rounding added)

PreOvr			1 bit
	- output from multiplier output
	- driven from combination logic after p-latch (Stage 2, 3)
	- used to determine rounding - Ovr bit

INPUTS
------

SelRnd0, SelRnd1	2 bits
	- input to multipler rounding logic - controls a*b/a*b+1 selection
	- drives to combinational logic that feeds an N latch. (Stage 2,3)
	- If integer mult, SelRnd1 = (Rs & Rc) | (Rs & lowcarry)
					| (Rc & lowcarry)
	- If floating mult, SelRnd1 = (lowcarry | ~RsRc) & (PreOvr | low63)
	- otherwise, value is unimportant
	- SelRnd0 = ~SelRnd1

Overflow, Overflow_L	2 bits
	- input to multipler rounding logic - controls shift-right
	- drives to combinational logic that feeds an N latch. (Stage 2,3)
	- if floating mult, Overflow = high53.  Otherwise, =0
	- Overflow_L = ~Overflow

RsRc, RsRc_L		2 bits
	- input to multipler rounding logic - adds in extra rounding bit
	- drives to combinational logic that feeds an N latch. (Stage 2,3)
	- if floating mult, RsRc = Rs | Rc.  Otherwise, =0
	- RsRc_L = ~RsRc

L0Force, L0Force_L	2 bits
	- input to multipler rounding logic - force L0 bit for round-to-even
	- drives to combinational logic that feeds an N latch. (Stage 2,3)
	- if floating mult, L0Force = ((~high53) & low63 & Sticky) |
	  (high53 & ~high0 & (~low63) & Sticky),
	- L0Force_L = ~L0_Force

FMUL, IMUL, HMUL, MULbyp, FMUL_L, IMUL_L, HMUL_L, MULbyp_L 	8 bits
	- input to selection mux after rounding logic
	- drives to combinational logic that feeds an N latch. (Stage 2,3)
	- if FMUL, FMULA, FMUL = 1, if HMUL, HMUL = 1, if IMUL, IMUL = 1,
	  otherwise MulByp = 1
	- FMUL_L = ~FMUL, HMUL_L = ~HMUL, IMUL_L = ~IMUL, MULByp_L = ~MULByp



********* Alignment stage control *********

OUTPUTS
-------

shfted<2:0>	3 bits
	- output from alignment shifter - R, G, and S bits of shifted result
	- driven by N-latch (Stage 4, 5)
	- used to determine adder rounding

INPUTS
------

alnBT_v0, alnNB_v0, alnQW_v0	12 bits
	- input to alignment stage specifying how far shift should go
	- drives combination logic that gets latched by a p latch
	- set to amount to shift argument - one hot encoding for each
	  set of 4 bits (IE, alnBT0 specifies no shift, alnBT1 specifies
	  1 bit shift, etc)

subtract, subtract_L		2 bits
	- input to alignment stage specifying if non-shfted number should be
	  inverted
	- drives combination logic that feeds a p latch
	- should be set if FADD (or FPMULA) & opposite signs, or FSUB
	  and same signs
	- subtract_L = ~subtract


********* Adder Rounding stage control *********

OUTPUTS
-------

nrnd<0>				1 bit
	- output from rounding stage specifying what L bit is equal to
	- comes from combinational logic after n latch
	- used to do round-to-nearest-even

det<3:0>			4 bits
	- output from rounding stage specifying which shift mode
	- comes from combinational logic after n latch
	- used to determine which number to add to LSB's.

neg_res				1 bit
	- output from rounding stage specifying whether result was negative
	- comes from combinational logic after n latch
	- used to correctly determine rounding

INPUTS
------

sub_del, sub_del_L		2 bits
	- input to add rounding stage specifying if correct factor of 1
	  should be added for subtracts.
	- drives combinational logic that feeds a p latch
	- should be set if FADD (or FPMULA) & opposite signs, or FSUB
	  and same signs
	- sub_del_L = ~sub_del
	- delayed version of above by 1 clock cycle.

ADD_Byp, ADD_AByp_L		2 bits
	- input to bypass mux in add rounting logic
	- drives combinational logic that feeds a p latch
	- ADD_Byp = 1 for fadds/fsubs/fpmula, 0 for multiplies
	- ADD_Byp_L = ~ADD_Byp
	
negFTOI, negFTOI_L		2 bits
	- input to add rounding logic to force negative avalue
	- drives combinational logic that feeds a p latch
	- negFTOI = 1 for FTOI command when floating point input is
	  negative, 0 otherwise
	- negFTOI_L = ~negFTOI

Arnd, Arnd_L			2 bits
	- input to select between A+C and A+C+1 in add rounding logic
	- drives combinational logic that feeds a p latch
	- Arnd = bit 3 of  (shfted[2:0] ^ 3{neg_res}) + neg_res + det[3:0]
	- Arnd_L = ~Arnd

AForceL0, AForceL0_L, AForceL1, AForceL1_L	4 bits
	- input to rounding logic to force L1 or L0 bit low
	- drives combinational logic that feeds a p latch
	- AForceL1 = ~det[3] & nrnd0 & ~new[2] & ~new[1] & ~new[0]
	  where new[2:0] is the result of the add for determing rounding
	- AForceL0 = ~det[2] & ~new[2] & ~new[1] & ~new[0]
	- AForceL1_L = ~AForceL1;
	- AForceL0_L = ~AForceL0;

********* Adder Rounding stage control *********

OUTPUTS
-------

NLZs				6 bits
	- output from normalization logic - number of leading zeros
	- arrives from combinational logic after a p-latch
	- used for postnormalization

zero				1 bit
	- output from normalization logic - is result zero?
	- arrives from combinational logic after a p-latch
	- used for postnormalization

INPUTS
------

Aoverflow, Aoverflow_L		2 bits
	- input to normalization stage - specifies right shift by 1 bit
	- drives combational logic before n latch
	- Aoverflow = det[3]
	- Aoverflow_L = ~Aoverflow

NormBT, NormNB, NormQW		12 bits
	- input to normalization stage - specifies left normalization shift
	- drives combational logic before n latch
	- one hot encoding of how much to left shift - more or less just
	  a simple encoding of NLZs, with a maximum for gradual underflow

lobits				2 bits
	- input to normalization stage - low two bits for shifter
	- drives combational logic before n latch
	- low 2 bits - R & G bits - for shifting in in case of normalization
	



From omv@ai.mit.edu Thu Sep 28 18:23:20 1995
Return-Path: <omv@ai.mit.edu>
From: omv@ai.mit.edu (Dan Hartman)
Date: Tue, 26 Sep 1995 18:32:28 -0400
To: skeckler@ai.mit.edu
In-Reply-To: <199509262224.SAA10014@kiwi.ai.mit.edu> (skeckler@ai.mit.edu)
Subject: Re: rest of signals

   From: skeckler@ai.mit.edu (Steve Keckler)
   Date: Tue, 26 Sep 1995 18:24:53 -0400


   What about: 

   stage 4:

   ShftAB, ShftC, PRESHFT2, DIFSIGN, DIFSIGN_L

   stage 5:

   DIFsigns, DIFsigns_L

   Also, can you take the signal names at the top level schematic that
   are almost the same and rename them so that there is no confusion.


DIFSIGN is now subtract
DIFsigns is now sub_delay

ShftAB, ShftC
	- input to alignment stage - controls which number gets shifted
	- drives to combinational logic that feeds a P latch. (Stage 2,3)
	- ShftC = ~ShftAB
	- ShftAB = appropriate one dependning on which exponent is
	  lower.  For integer multiplies, ShftAB = 0

PRESHFT2
	- input to alignment stage - shift for ITOF when top bits are positive
	- drives to combinational logic that feeds a P latch. (Stage 2,3)
	- PRESHFT2 asserted when either bit 63 or bit 62 contains a 1.
	  normally deassrted when not doing ITOF

(note:  Schematics are incorrect for PRESHFT 2)


From omv@ai.mit.edu Thu Sep 28 18:23:29 1995
Return-Path: <omv@ai.mit.edu>
From: omv@ai.mit.edu (Dan Hartman)
Date: Thu, 28 Sep 1995 14:01:05 -0400
To: skeckler
Subject: two new signals on alignment stage


ext and ext_L are signals that feed the shifter.  Basically, ext is
low EXCEPT when doing an ITOF where the integer is negative, in that
case, you want to feed in a 1 to sign extend.

-dan


