%* Last edited: May 31 16:01 1996 (misha)
\section{Architectural Design}

There has been a considerable amount of research on architectures for image
processing and image understanding.  A variety of processor designs and
interconnection networks have been proposed (and far fewer have been
implemented).  This review concentrates on SIMD designs and on alternate
approaches with comparable performance.

Early examples of machines designed for image processing include Goodyear's
MPP\cite{Potter85}, NCR's GAPP \cite{Cloud88}, and ICL's DAP.  The most
widely produced SIMD machine was Thinking Machines' CM-2. A contemporary
commercial product was produced by MasPar \cite{Blank90}, and recently
upgraded to the MP-2 \cite{Kim93}.

There are also several research designs which have not been put into
commercial production.  These designs explored different aspects of SIMD
architectures. For example, IBM's polymorphic torus \cite{Li89}
concentrated on adding connection autonomy by the addition of locally
reconfigurable network switches.  The MCNC Blitzen project \cite{Blevins88}
updated the original MPP design for VLSI technology by adding on-chip RAM,
local modification of addresses, and an X-grid 8-neighbor interconnect. A
unique Some/None network intended for associative processing was stressed
in the CAAAP architecture \cite{Shu89} developed at the University of
Massachusetts at Amherst. As in the polymorphic torus, network switches
were locally controlled, but groups of processors could be electrically
connected.  This feature allowed efficient connected components and global
statistics algorithms.

A number of recent research efforts promise to achieve substantially higher
performance than these early designs.  A 256-element SIMD array driven by
an on-chip RISC-like processor has been designed at the University of
Sheffield \cite{Thacker94}.  The performance is reasonable, given the
number of processors, but is limited by the instruction issue rate of the
RISC controller, the low I/O bandwidth, and the lack of off-chip memory
support.  A major US semiconductor manufacturer\footnote{Psst: Motorola} is
readying an as yet unannounced SIMD processor design with 50 MHz clock
rates and sixty-four 8-bit processors for use in embedded multimedia
applications.  The Supercomputer Research Center has developed a
processor-in-memory chip which augments a 128 Kbit SRAM array with
bit-serial processors at each row \cite{terasys}.  The performance of this
design is rather low due to the small number of PEs and modest clock rate.


An alternate processor-in-memory MIMD/SIMD architecture has been developed by
IBM \cite{execube}.  The Execube chip incorporates 8 16-bit PEs, each with
64 KB of DRAM memory, and can be operated in SIMD mode from a global
instruction bus. The performance is again rather low due to the long cycle
time of DRAM and because instructions are stored in the same memory as data.

An integrated micro-MIMD chip, integrating 48 16-bit processors and an
interconnection network on each chip has been designed at UC Berkeley
\cite{berkeley-dsp}.  The IC delivers an impressive 2.4 GOPS on a variety
of DSP algorithms and is designed to communicate efficiently with other
chips.  However, since each PE's instruction memory is only 8 words deep,
with no provision for expansion, the architecture is not suitable for more
complex algorithms.


A class of DSP chips, most notably the Texas Instruments C40 and the Analog
Devices SHARC processors, have been designed to support efficient execution
over data arrays and inter-processor communication.  These appear more
promising than the RISC based systems, but still lack performance and waste
power.


Another technology that delivers comparable performance to Abacus and PADDI
is the use of reconfigurable logic as exemplified by Field Programmable
Gate Arrays. An array of programmable logic can be used to configure
applications specific hardware and thereby obtain excellent performance. For
example, research at DEC Paris have implemented algorithms ranging from
Laplace filters to binary convolutions [PAM].
If the per-chip performance is computed as aggregate performance divided by
the number of FPGA chips in the system, each Xilinx chip delivers
approximately 500 million 16-bit operations per second. 

\begin{table}[htbp]
  \small
\begin{center}
\begin{tabular}{|l|r|r|r|r|r|r|r|}
\hline
Machine        & Performance    & Clock  & I/O  BW & \multicolumn{2}{|c|}{Mem BW}  &  Tech \\
               & 16-bit MOPS &  MHz & MB/sec     & Internal & External &  $\mu$ \\
\hline 
TMC CM-2        &   8     &   8   & 8           &   32 & 16       &  1.5   \\
SRC TeraSys      &  20     &  10   & 5           &   80 & 5      &  1  \\
IBM EXECUBE      &  50     &  25   & 300         &  400 & 0      & .8  \\
TI C40           & 50      &  50   & 200         &  0 & 200        &  .8 \\
MasPar MP-2      & 133     & 12.5    & 45     & 1600 &  45 &   1 \\
HP8000           & 200     & 200   & 800          &  0 & 960        &  .5 \\
Sheffield  DIP   & 320     &  40   & 160     & 2560 & 0        &   1
\\
Xilinx XC3090    & 500     & 20 & NA & NA & NA & 1 \\
Berkeley PADDI-2 & 2400    &  50    & 800       &  14400 & 0    &  1
\\
%%MIT Matrix       & ?    &  ?    & ?      &  ? & ?   &  ?  \\
{\bf MIT Abacus-1}     & {\bf 2000}    &  125  & 1000     &  32000 & 512  &  1  \\
\hline
\end{tabular}
\end{center}
\caption{Architectural performance comparison}
\label{tab:perfcomp}
\end{table}


%Table~\ref{tab:perfcomp} clearly shows that no other design has the
%combination of flexibility, raw performance, communication bandwidth, and
%I/O bandwidth required for an effective parallel system.


%We have described a number of other approaches to obtaining high
%performance in the Summary section. Since an overwhelming amount of
%research is already being done commercially on improving the performance of
%RISC processors and DSP chips, we will focus on less mainstream research.

It is unfair to directly compare the 16-bit performance of Abacus compared
to the wider-width Execube and MasPar PEs, as they  incorporate
floating-point support.  However, even granting a factor of five in area,
their performance is still lagging. Both of these designs make the classic
mistake of single-porting their register files.  The implication of
requiring three cycles to perform a single instruction is that three times
the area could have been allocated to triple-porting the memory. And the
area in this case refers to the \emph{entire} silicon area, including
communication pads and support circuitry.

The only architecture comparable in performance is the Berkeley PADDI-2
chip, and it is not suitable as a general computing element as it can only
store eight instructions per PE.  Of course, when the computation task can
be expressed as piping data through a systolic array, the IC is an ideal
high-performance, low chip-count solution.

We are not aware of any other research SIMD machine that even approaches
the Abacus design in terms of performance per silicon area on low-precision
integer operations.  Our advantage occurs for a variety of reasons,
including an aggressive clock rate of 125 MHz, made possible by careful
custom design, high density manual circuit layout, and the inherent
advantage of RBP operations.

\paragraph{MGAP}. Also reconfigurable. The authors state unreasonable
expectation about transitioning to 100 MHz operation from expected 50~MHz
(internal).

\subsection{Reconfigurable Computers}

The Illiac-IV, had 64 64-bit PEs that could be partitioned as 128 32-bit
PEs or as 512 8-bit PEs.  Interestingly, modern processors have
rediscovered this trick under the name of multimedia acceleration.  Over 30
years after same technology debuted in the Illiac-IV, Intel's MMX and
UltraSparc's VIS instruction architectures recognize the advantage of
reconfigurability.



The idea of an RBP architecture is not completely new. Even the first
massively parallel machine, the DAP, allowed columns of PEs to be
configured into a ripple-carry chain.  This capability was not central to
the architecture and operated slower than bit-serial operations.  The
reconfigurable processor array (RPA) \cite{Rushton89} uses a mixed approach
to RBP.  Although each PE processes two bits at a time, and a data word is
shared among a PS, considerable hardware resources are devoted
to supporting bit-slice operations.  As a result, each PE is quite complex
for a fine-grained machine.


\section{High Speed Design}

Rockoff points out other skew components:
\begin{itemize}

\item Cable length
\item PE board driver delay 
\item PCB trace length variations
\item Impedance variations on PCB
\item Rise time variations due to stub length variations.

Concludes that variations can be as high as 7.0 ns.

Worries about amount of work to be done by the controller and its
speed.

Worries about power consumption of parallel terminated lines.

About latency caused by the pipeline stage additions.


\end{itemize}

