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\chapter{Discussion}

Now that the design has been discussed and the analysis is complete, it is
time to step back and examine what was learned in the process, how the
newly found knowledge may be applied, and future research based on this
work.~\footnote{So sit back, light up a stogie, and read on.}

\section{Chip Design}

The chip design process has served a number of purposes.  Theoretical
analysis or simulations would have been insufficient to conclusively
demonstrate the soundness of the design.  The act of fabricating an
artifact and measuring consumed area and execution speed produced a number
of important lessons.

Abacus has demonstrated that high clock rates are achievable with simple
circuits, even in a slow process technology.  Although this demonstration
should not be surprising, since near-gigahertz level bit-serial adders have
been fabricated in comparable technologies, the SIMD architecture community
has not internalized this lesson.  The Abacus design demonstrates the
performance gains achievable in SIMD systems through the use of high-speed
VLSI techniques and raises the bar for future architectural development.

Abacus has provided a framework for future chips design.  Having accounted
for all the major system issues dealing with high-speed SIMD design, Abacus
can serve as a checklist for designers.  The analysis of memory size and
ALU complexity provides designers with a design tool more quantitative than
experience and intuition for architecture development.  And this design has
exposed a number of ``fallacies and pitfalls,'' such as ``ALUs should
always be small and fast'' and ``PEs should have as much memory as
possible.''~\footnote{These may not be the best examples, but I'm sure you
  can think of better ones.}

The experience gained through the Abacus design also suggests that the
developer design a processing element and immediately develop the
instruction and data distribution network {\em before\/} performing circuit
optimizations, since the global structure will affect the PE in potentially
unanticipated ways.  Identifying possible optimizations using software
compensation of layout quirks and removal of abstraction boundaries for
layout improvement are also possible only when the global PE structure is
well defined.

Some of the lessons learned are apparently the same as those discovered by
the mainstream architecture community.~\footnote{Which is interesting
  considering how far outside the mainstream we are.} The instruction
distribution and sequencer limitations are similar to the microcoded CISC
processors' speed limitations. The current Abacus design is comparable to a
first or second generation RISC design. As clock speeds rise due to
architectural innovation and improvements in circuit design, power
dissipation becomes a significant issue. The transition to this
power-sensitive regime occurs more quickly for a SIMD machine since unlike
a uniprocessor, many power-hungry ICs share a board and must be cooled. The
next Abacus design must therefore pay more attention to power dissipation.

Fortunately, much of the power in a SIMD system such as Abacus is
dissipated in very regular, highly capacitive structures such as instruction
wires. These structures are suitable for novel power saving techniques such
as partial energy recovery.

\section{System Design}

\section{Algorithmic Analysis}

The application of the set of DARPA IU and other benchmarks to Abacus has
elucidated the difference between virtual emulation of conditional
algorithms.  Algorithms that use nested parallel {\em where\/} clauses
require relatively expensive storage of the {\em active\/} bit between
context switches.  This costs both time and memory capacity.

The analysis has underscored the need for understanding memory requirements
as well as time requirements of algorithms.  Given the enormous difference
in access times between on-chip and off-chip memory, algorithms with
theoretically poorer performance but a smaller working set can outperform
supposedly efficient but memory-intensive algorithms. A true algorithmic
figure of merit must include assumptions about the underlying machine
model.

\section{Architectural Analysis}

A number of research projects concern implementing DRAM-based SIMD devices
\cite{Gealow96}.  Surprisingly, these designs still use bit-serial
processors.  A section FOO has already pointed out the disparity between
memory access time and the amount of time spent computing by a one-bit
adder.  The disparity is worse by an order of magnitude when DRAM access
times reach 50~ns. Having paid an extraordinary amount of time for the
access, the ALU should extract as much computation as possible from the
data before writing it back.  In general, a good rule of thumb is that the
slower the memory, the more complex the ALU.

In another example, the MGAP-2 design~\cite{mgap2} relies on a redundant
representation to avoid carries. Yet at the targeted clock rate of 50~MHz
in a 1~micron VLSI technology, the carry can easily ripple through 16 bits.

The inverse effect can be seen if fast DRAM cells are developed. An early
design for the Abacus memory was based on dense, fast, DRAM cells. If this
approach is adopted, what is the effect on the optimal datapath width?  The
ALU area is increased relative to the memory, and therefore assigns a
higher penalty to wider datapaths.

Analysis of the Abacus architecture has led to the insight that
area-efficient memory systems require at least four edge times to execute a
memory access. ALU delays must be at least as long as that time interval.
Since this time is already greater than that required for a four-bit ripple
carry adder, and edge times will increase with improved VLSI technology
(and therefore smaller feature sizes), we may proclaim bit-serial designs
dead, at least for memory-based PEs.

The passing of bit-serial processors appears even more inevitable when
pipelined processing is considered. Since pipeline stage delays are
(ideally) equal, the execute part of the cycle does almost no work for the
same reason as in the unpipelined case. Even worse, the overhead of
pipelining registers and forwarding logic comes with no performance gain
and therefore decreases performance for narrow-width datapaths.

Another obvious observation from the first-order model is that low-memory
PEs deliver higher performance (for applications that fit in memory). In
the limit, processors with no memory offer the very highest performance,
which explains why FPGAs perform so well: if the algorithm can be converted
into a systolic form with little storage per processing node, then all of
the silicon is busy computing.  If the algorithm run on a low-memory chip
requires many off-chip memory references, system performance becomes equal
to memory access speed.

\section{Observations}

SIMD processors are beginning to enter into the everyday computing realm
under the guise of multimedia processors.  For example, Chromatic's Mpact
chip contains 8 9-bit processors operating in SIMD mode.

\section{Parting Remarks}

First, the Abacus project tested the limits of the premise that simple
one-bit PEs allow a faster overall clock rate. Although this is a common
argument in research papers, other MPP SIMD systems use a clock rate
substantially slower than that of commercial bit-parallel microprocessors.
The 125~MHz Abacus chip clock is the highest of any of the massively
parallel SIMD systems in the literature.  Further increases in clock speed
are limited by instruction bandwidth rather than PE complexity, and
therefore transfer the difficulty to off-chip interfaces and printed
circuit board design.  Maintaining clock speed while increasing the work
done per cycle holds more promise as the approach for incorporating smaller
and faster VLSI technology.

Second, analysis determined how effectively a collection of simple one-bit
PEs could emulate bit-parallel hardware. As shown in Section~4, a variety
of arithmetic circuits can be emulated at a cost of two to five cycles.
However, while reconfiguration reduces the silicon cost, it increases the
time requirements in two ways. Bit-level reconfiguration precludes hardware
pipelining by introducing dependencies on network switch settings.
Conventional techniques for dealing with data dependencies (such as
forwarding) cannot be used. Additionally, reconfiguration overhead is a
significant fraction of arithmetic operation times.  The next multi-bit
bit-slice design effort intends to address these issues.

Third, completion of an entire system brought to light any unexpected
bottlenecks and performance hits in high-speed SIMD designs.  Consideration
of board-level issues led to the development of instruction retiming logic,
high-speed mesh signaling, low pin-count data I/O, and software control
over DRAM timing.  Abacus now has a system framework that allows
modification of the PE core while retaining plug compatiblity with the rest
of the machine. Since the clock rate is already aggressive, it may be held
steady for a number of years while researching how to complete more work
per cycle.

From a theoretical viewpoint, the Abacus implementation provides a set of
realistic constants that can be used to evaluate reconfigurable mesh
algorithms.  The aggressive (in terms of speed and integration) nature of
the design explores physical limitations on architecture that will become
more significant in the future. For example, it is becoming obvious that
chip boundaries cannot be abstracted away in the interests of software
regularity.

Specialized architectures have fallen out of favor as commercial pressure
continually drives up the performance of general purpose microprocessors.
The current trend in parallel architecture is to construct parallel systems
from slightly modified commodity processors.  

The Abacus project, through this dissertation, has shown that for the
problem domain of early vision, parallel computers based on a SIMD
reconfigurable bit-slice architecture can outperform those based on
conventional processors by over an order of magnitude using the same
silicon resources.


