% -*- Mode: LaTeX;  -*-
% File: howfast.tex
% Author: Mike Bolotski (misha@ai.mit.edu)
% Copyright (C) Artificial Intelligence Laboratory, 1996
%*-------------------------------------------------------------------------
%* FUNCTION:
%*
%* CLASSES:
%* 
%* RELATED PACKAGES:
%*
%* HISTORY:
%* Last edited: Sep  5 17:26 1996 (misha)
%* Created: Wed Sep  4 19:41:15 1996 (misha)
%*-------------------------------------------------------------------------
\section{Design Style}

The high clock speed of the Abacus-1 chip is due to careful circuit design
and physical layout. This section identifies the factors that contributed
to fast execution.

\paragraph{Layout Style.} The processing element was implemented entirely
in full custom using the Cadence tool suite. A number of small standard
cells used in the control logic were synthesized from schematics.  The
control section, including instruction decoding and TAP control, was
assembled from these cells and interconnected with a greedy router locally
developed by Larry Dennison.  The router introduced some layout violations,
and those errors were manually corrected.

Layout synthesis was also used in creating the scan registers surrounding
the instruction decode, but this turned out to be a mistake. A rough
estimate indicates that a manual layout would have required approximately
the same amount of design effort, and would have achieved almost 30\% area
reduction.

A substantial contributor to layout density was the use of vendor-specific
layout rules instead of the common scalable design rules provided to
universities by MOSIS.  The effort invested in customizing the Cadence
tools to the Hewlett-Packard technology was quickly repaid, as the area
penalty due to scalable rules is estimated at 40\%, especially for full
custom layout.

%% Dense layout decreases wire length and parasitic capacitance.

\paragraph{Circuit Design.}

A number of design principles independent of layout optimizations
contributed to the high clock speed.
\begin{enumerate}

\item Dynamic logic was used extensively in the ALUs, network configuration
  decoder, and the network pathway itself. 

\item As a corollary, the design was optimized to use mostly NFETs for
  pass gates and precharge transistors.  Not only are N devices smaller,
  leading to denser layout, but they also load the control signal more
  lightly.


\item Global signals were carefully distributed by the use of matched
  wiring, driver buffers, and dummy logic elements.  As a result, timing
  was more predictable, enabling smaller timing margins.

%% \item Many control wires allow large buffers to drive them.

\item Some circuit elements were used for multiple purposes. For example,
  precharging bitlines through the column select transistors required only
  one precharge transistor per bus, instead of one per bitline.


\item Noise margins were sacrificed where necessary. For example,
  the bitlines were precharged to a $V_T$ drop below $V_{dd}$. Also,
  inverters were ratioed based on preferred transistion directions. Thus, 
  if a particular node was precharged high and evaluated low, the
  corresponding inverter was ratioed to switch at a higher voltage.

\item Dynamic latches were used to capture data and allow the previous
  stage to be reset as soon as the data was latched. This increased the
  effecive recovery time.

\item Signal buffering was optimized both at the schematic and layout
  levels.  A tool was written to probe a wire in a schematic and calculate
  its total capacitive load. As the design changed, the program constantly
  recalculated optimal buffer sizes. A layout macro was optimized to
  generate a fingers-style layout \cite{Weste93}, greatly reducing
  parasitic diffusion capacitance.


\end{enumerate}


\paragraph{Functional Optimizations.}

Some performance optimizations relied on the use of software to compensate
for layout quirks. For example, reading from the network port produced the
inverse of what was written. Correct execution depended on the assembler
to detect the network port as one of the sources and modify the ALU
operation, relying on the flexibility of the ALU to generate a compensating
function.

Another class of optimizations arose as a result of removing abstraction
boundaries.  For example, reading from the $\overline{\mbox{bit}}$ bus
results in inverted values, but this value need not be corrected until it
reaches the ALU inputs, and there the correction need not add an inverter
delay but simply reverse the outputs of a local buffer.





