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\contentsline {figure}{\numberline {3-1}{\ignorespaces RBP Organization}}{32}
\contentsline {figure}{\numberline {3-2}{\ignorespaces Silicon Efficiency Ratios}}{33}
\contentsline {figure}{\numberline {3-3}{\ignorespaces Processing Element Block Diagram}}{34}
\contentsline {figure}{\numberline {3-4}{\ignorespaces Network cell}}{34}
\contentsline {figure}{\numberline {3-5}{\ignorespaces Shift}}{36}
\contentsline {figure}{\numberline {3-6}{\ignorespaces Accumulate}}{37}
\contentsline {figure}{\numberline {3-7}{\ignorespaces Addition}}{38}
\contentsline {figure}{\numberline {3-8}{\ignorespaces Compare}}{38}
\contentsline {figure}{\numberline {3-9}{\ignorespaces A +-reduce operation.}}{40}
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\contentsline {figure}{\numberline {4-1}{\ignorespaces Memory read and write path (one of the banks)}}{44}
\contentsline {figure}{\numberline {4-2}{\ignorespaces Pad ring picture}}{47}
\contentsline {figure}{\numberline {4-3}{\ignorespaces Evaluation of an arbitrary 3-input function by a two-input ALU. Two auxiliary memory locations are required.}}{47}
\contentsline {figure}{\numberline {4-4}{\ignorespaces Different network styles.}}{49}
\contentsline {figure}{\numberline {4-5}{\ignorespaces Various network configurations. Grid communications mode (north). Bit broadcast. Arithmetic.}}{50}
\contentsline {figure}{\numberline {4-6}{\ignorespaces Network Block Diagram}}{51}
\contentsline {figure}{\numberline {4-7}{\ignorespaces Network Accelerator}}{52}
\contentsline {figure}{\numberline {4-8}{\ignorespaces Memory read and write path (one of the banks)}}{52}
\contentsline {figure}{\numberline {4-9}{\ignorespaces PE Layout}}{54}
\contentsline {figure}{\numberline {4-10}{\ignorespaces PE Layout}}{54}
\contentsline {figure}{\numberline {4-11}{\ignorespaces Abacus PE Timing}}{58}
\contentsline {figure}{\numberline {4-12}{\ignorespaces DLL Arbiter}}{59}
\contentsline {figure}{\numberline {4-13}{\ignorespaces Instruction Pad}}{61}
\contentsline {figure}{\numberline {4-14}{\ignorespaces Dummy Chip Photograph}}{66}
\contentsline {figure}{\numberline {4-15}{\ignorespaces Time Ring Unit}}{68}
\contentsline {figure}{\numberline {4-16}{\ignorespaces Hearbeat Monitor}}{73}
\contentsline {figure}{\numberline {4-17}{\ignorespaces IO Burst}}{74}
\contentsline {figure}{\numberline {4-18}{\ignorespaces DP Shift}}{75}
\contentsline {figure}{\numberline {4-19}{\ignorespaces DP Shift}}{76}
\contentsline {figure}{\numberline {4-20}{\ignorespaces DP Shift}}{77}
\contentsline {figure}{\numberline {4-21}{\ignorespaces Grid Shift}}{78}
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\contentsline {figure}{\numberline {5-1}{\ignorespaces System Block Diagram}}{80}
\contentsline {figure}{\numberline {5-2}{\ignorespaces Sequencer Block Diagram}}{81}
\contentsline {figure}{\numberline {5-3}{\ignorespaces Interleaved scalar and parallel code}}{82}
\contentsline {figure}{\numberline {5-4}{\ignorespaces PE Board}}{83}
\contentsline {figure}{\numberline {5-5}{\ignorespaces Reformatting Circuitry Block Diagram}}{86}
\contentsline {figure}{\numberline {5-6}{\ignorespaces Edge Detection Example}}{89}
\contentsline {figure}{\numberline {5-7}{\ignorespaces Optical Flow Example}}{90}
\contentsline {figure}{\numberline {5-8}{\ignorespaces Optical Flow Field}}{91}
\contentsline {figure}{\numberline {5-9}{\ignorespaces K-curvature definition}}{93}
\addvspace {10pt}
\contentsline {figure}{\numberline {6-1}{\ignorespaces Foo}}{100}
\contentsline {figure}{\numberline {6-2}{\ignorespaces Foo}}{101}
\contentsline {figure}{\numberline {6-3}{\ignorespaces Foo}}{103}
\contentsline {figure}{\numberline {6-4}{\ignorespaces Foo}}{104}
\contentsline {figure}{\numberline {6-5}{\ignorespaces Foo}}{105}
\contentsline {figure}{\numberline {6-6}{\ignorespaces Foo}}{107}
\contentsline {figure}{\numberline {6-7}{\ignorespaces Foo}}{108}
\contentsline {figure}{\numberline {6-8}{\ignorespaces Foo}}{109}
\contentsline {figure}{\numberline {6-9}{\ignorespaces Foo}}{111}
\contentsline {figure}{\numberline {6-10}{\ignorespaces Foo}}{112}
\contentsline {figure}{\numberline {6-11}{\ignorespaces Foo}}{113}
\contentsline {figure}{\numberline {6-12}{\ignorespaces Probability of an on-chip hit sequence of length $k$ for different values of $p$, the miss probability. Note that for high $p$ almost all the area under the curve is near small values of $k$, and therefore long load times. }}{114}
\contentsline {figure}{\numberline {6-13}{\ignorespaces [}}{115}
\contentsline {figure}{\numberline {6-14}{\ignorespaces Execution time as function of $m$. The dip in the middle is the effect of background loading. Without it, the graph would have continued in a straight line. Notice that the dip occurs at a non-useful $m$ value, as it is difficult to evenly partition a 16-bit value.}}{120}
\contentsline {figure}{\numberline {6-15}{\ignorespaces Execution time as function of m and bandwidth}}{121}
\addvspace {10pt}
\contentsline {figure}{\numberline {7-1}{\ignorespaces Abacus-2 Interconnection}}{130}
\contentsline {figure}{\numberline {7-2}{\ignorespaces Abacus-2 Mesh Network}}{135}
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