\addvspace {10pt}
\addvspace {10pt}
\contentsline {table}{\numberline {2.1}{\ignorespaces Architectural performance comparison}}{22}
\addvspace {10pt}
\contentsline {table}{\numberline {3.1}{\ignorespaces Single Chip Arithmetic Performance}}{40}
\addvspace {10pt}
\contentsline {table}{\numberline {4.1}{\ignorespaces Table 1 Silicon area requirements of the single-banked, single-ALU design and the double-banked, double-ALU design. As expected silicon area increases by only 15\%.}}{46}
\contentsline {table}{\numberline {4.2}{\ignorespaces Number of cycles required for common operations in horizontal mode. The count includes reconfiguration cost.}}{48}
\contentsline {table}{\numberline {4.3}{\ignorespaces PE Area Resources}}{53}
\contentsline {table}{\numberline {4.4}{\ignorespaces RC delay calculation.}}{55}
\contentsline {table}{\numberline {4.5}{\ignorespaces Chip Area by Subsystem}}{67}
\contentsline {table}{\numberline {4.6}{\ignorespaces Pin Requirements.}}{68}
\contentsline {table}{\numberline {4.7}{\ignorespaces Board Stackup}}{71}
\contentsline {table}{\numberline {4.8}{\ignorespaces summary of tested structure}}{74}
\addvspace {10pt}
\contentsline {table}{\numberline {5.1}{\ignorespaces Board Level Parts Count}}{84}
\contentsline {table}{\numberline {5.2}{\ignorespaces Reformatter Part Count}}{87}
\addvspace {10pt}
\contentsline {table}{\numberline {6.1}{\ignorespaces Analytical Model Parameters}}{98}
\contentsline {table}{\numberline {6.2}{\ignorespaces Fraction of Operation Costs Affected by Data Path Width}}{102}
\contentsline {table}{\numberline {6.3}{\ignorespaces Fraction of Operation Costs Affected by Data Path}}{102}
\contentsline {table}{\numberline {6.4}{\ignorespaces Architectural and Algorithmic Parameters}}{117}
\contentsline {table}{\numberline {6.5}{\ignorespaces Pad Ring Organizations}}{124}
\addvspace {10pt}
\contentsline {table}{\numberline {7.1}{\ignorespaces Abacus 2 Pin Budget}}{137}
\contentsline {table}{\numberline {7.2}{\ignorespaces Abacus-2 PE Area}}{138}
\contentsline {table}{\numberline {7.3}{\ignorespaces Abacus-2 Chip Spec}}{138}
\addvspace {10pt}
\contentsline {table}{\numberline {.1}{\ignorespaces Microinstruction Types}}{145}
\contentsline {table}{\numberline {.2}{\ignorespaces DRAM Timing Information}}{149}