\paragraph{VRAM} Dual Port Video RAM which combines DRAM and SAM (serial access memory) as display buffer in a single chip and seperates refreshing bus from rendering bus. However, the serial prot cycle time of the VRAM is as much as 25ns (40MHz) and die area is about 50\% larger than the standaard DRAM. \paragraph{EDO} Extended Data-Out DRAM improves the data rate of the conventional page-mode DRAM with a small change of the output buffer control. In the normal page mode, output data becomes invalid at the end of a column address strobe. This narrow output window prevents the operating frequency from exceeding 25 MHz. The EDO mode keeps output data valid until next column address strobe begins. Thus the data latching becomes easier and it enables shorter cycle time. Because this mode requires minimal changes to existing interfaces, people expect it soon to become popular and replace conventional DRAM. EDO DRAM will be used as main memory as well as low-end graphic memory. However, this interface limits the data rate to 40 to 50 MHz. Burst EDO: EDO and counter to transfer a linearly adressed string of data. \paragraph{SDRAM} Synchronous DRAM features serial read/write operation synchronized with an external clock. Either pipeline operation or on-chip parallel-serial conversion with multiple registers realizes high speed burst data transfer. The system can access up to 8-bit serial data in one column cycle. During a serial read, next-column address loading in page mode enables the next 8-bit read without a gap. Two-bank interleaving enables gapless access to a different row of the other bank. SDRAM had a mode register that programs burst length, burst type, CAS latency, and so on, to accommodate different system requirements. Although it deffers from conventional asynchronous DRAM, JEDEC (the Joint Electronic Devices Engineering Council) has standardized SDRAM, and it is expected to be the next standard DRAM after EDO. SDRAM will supprot systems from 60 to 150 MHz. Pipelined SDRAM requires only a slight modification to the conventional DRAM architecture-at the expense of operating frequency. This frequency limit will prevent pipelined SDRAM from operating at the ultrahigh speed next-generation microprocessors will require. On the other hand, the multiple-registerd architecture relaxes internal signal traffic, and designers can therefore apply it to 64-Mbit SDRAMs and beyond with increasedd data rates. A 128-register, 16-Mbit SDRAM fabricated with a 0.55-um CMOS process demonstrated 180-MHz operation. The architecture increased the memory array area about 1.5 percent over the conventional array. \paragraph{CDRAM} Cached DRAM has a localized, on-chip cache with a wide internal bus composed of two sets of static data transfer buffers between cache and DRAM. The architecture realizes concurrent operation of DRAM and SRAM syschronized with an external clock. In CDRAM, seperate control and address input terminals of the two portions enable independent control of the DRAM and SRAM. The DRAM portion has page mode access capability. The data transfer buffers consists of two sets of 16-byte buffers. As a result, the system achieves continuors and concurrent operation of DRAM and SRAM. It keeps a cache miss operation in the background of the cache hit cycles, and a streamless data stream can be obtained with SRAM access time. \paragraph{RDRAM.} Rambus DRAM performs an enhanced, on-chip, parallel-serial conversion with two-bank interleaved similar to that of the registered SDRAM. it also features an on-chip phase-locked loop and a Rambus I/O interface that has a 600-mV swing with termination and protocal. It operates at 250 MHz with data transferred both on the rising and falling edges of its clock, giving a data transfer rate of 500 Mbit/sec. per wire. The system employs a packet transfer method to reduce pin count. After sending a request packet, in one access period it obtains up to 256 bytes of serial data at 2ns/byte from 9-bit bus.The small pin count eases the board layout design and the ASIC controller. RDRAM will require large standby and operating power consumption to maintain 250-MHz operation. \paragraph{EDRAM}. Enhanced DRAM adds small, distributed row cache buffers to the DRAM array. This addition hides the array precharge time and enables high-speed operation. Also, an on-chip latch (posting register) improves the write operatin in write-through mode. While EDRAM has a faster row access time than the conventional DRAM, it preserves the conventional DRAM interfaces as much as possible, including asynchronous operatin that provides easy conversion. This may limit future enhancement. The EDRAM has a small effective cache size due to the distributed cache architectue. \paragraph{SDRAM} IBM Microelectronics' 16Mbit SDRAM has been sampling and undergoing qualification since 4Q95. IBM has had reported success manufacturing a 100MHz SDRAM with no die penalty, underscoring the firm's desire to focus on high-end workstations. IBM also plans a 75MHz and 83MHz 16Mbit DRAM from the same die . EBN, 4/15/96, p 18. Discusses the evolutionary alternatives. Evolutionary DRAMs embody changes to the DRAM interface that are more substantive than those of the conventional alternatives. However, the DRAMs still preserve the separate data and multiplexed address buses. The evolutionary alternatives are Burst EDO (BEDO) DRAMs, Enhanced DRAMs (EDRAMs), Synchronous DRAMs (SDRAMs), and Cached DRAMs (CDRAMs). Describes the revolutionary alternatives, which offer a complete redesign of the DRAM interface. Both Rambus DRAMs (RDRAMs) and RamLink/SyncLink DRAMs replace the data and multiplexed address buses with one or two high-speed byte-wide interfaces that carry all address, data, and -signaling information. In late 1994, portions of the DRAM vendor community noticed the existence of RamLink and took an interest in it. Since then, a derivative of RamLink, called SyncLink, has been partially defined. An industry consortium has formed to commercialize and standardize a specification in advance of SyncLink DRAMs (SLDRAMs) devices coming to market. SyncLink is described in Section 8.4. Chapter 10 now contains significant analysis focussed on memory system design for high-performance embedded systems, including set-top boxes, video games, and DSP systems. These systems are all characterized by small memory sizes as well as high peak and sustained bandwidth requirements. \paragraph{Rambus} Despite its high performance, an RDRAM-based memory system dissipates less power than an SDRAM-based one. The RDRAM interface consumes more power (e.g., 0.5 W compared with 0.3 W), but the RDRAM memories consume only 0.8 W compared with 1.4 W for the SDRAMs. Consequently, the Rambus subsystem takes 1.3 W of power compared with 1.7 W for the SDRAM subsystem.