%* Last edited: Sep 5 02:09 1996 (misha) % -*- Mode: LaTeX; -*- \chapter{Abacus-1 Instruction Format} A 61-bit microcode word is used to transfer instructions into the PEs. The instruction pins are double cycled, so there are 31 pins. There are two types of instructions: {\em regular \/} and {\em special\/}. A special instruction is used to load control registers, generate load/store commands to the IO port, load an immediate constant, etc. A regular instruction consists of explicit ALU operations and addresses. Both instruction types contain a field of timing information for the DRAM interface. The upper 15 bits of each instruction contain this information and additional control information. \footnote{Some of these bits may be eventually replaced by configuration registers.} Special instructions are encoded by specifying an ALU operation of {\tt Clear} for the left ALU (bits 8-10 of the instruction word). In this case, the read addresses are irrelevant. The compiler enforces the convention that unused addresses for {\tt Clear} instructions are set to 0. The decoder detects the case of a {\tt Clear} ALU operation with a non-zero read address, and uses the lower four bits of the read address as the instruction type. Three bits are currently needed; the fourth is reserved for future expansion. During the execution of a special command, the PE array executes a NOP instruction (actually, the PE write clock is suppressed). \begin{table}[htbp] \begin{center} \begin{tabular}{|l|l|l|} \hline \hdr{Op Code} & \hdr{Name} & \hdr{Operation} \\ \hline 0000 & & Regular instruction \\ XX01 & LI & Load immediate constant \\ 1100 & LCR & Load control registers \\ 0010 & SARI & Set DRAM address register, Inst\\ 0110 & SARD & Set DRAM address register, DP\\ 1010 & LIO & Load from IO port \\ 1110 & SIO & Store to IO port \\ \hline \end{tabular} \end{center} \caption{Microinstruction Types} \end{table} The instruction format descriptions below do not include the DRAM timing field (bits 46-60). \section{Regular Instructions} A regular instruction consists of 6 addresses (4 read, 2 write), and 2 8-bit op-codes. %There are two other signals: {\em precharge-enable\/}, %which enables the network precharge in the next cycle (this can be omitted %by detecting a write to the NetOut address), and {\em override-idle\/}, %which performs a write regardless of the state of the {\tt idle \/} register. \def\bit#1{\multicolumn{1}{r}{\footnotesize #1}} \def\stopbit#1{\multicolumn{1}{r}{\footnotesize 46-#1}} \begin{tabular}{|l|l|l|l|l|l|l|l|l|} \hline Pad direction & RW & RRB & RRA & RALU & LW & LRB & LRA & LALU \\ \hline \bit{46} & \bit{41} & \bit{36} & \bit{31} & \bit{23} & \bit{18} & \bit{13} & \bit{8} & \bit{0} \\ \end{tabular} The ALU fields are the 8-bit ALU opcode specifications; RA and RB are the two read addresses, and W are the write addresses. The {\tt PadDir} bit indicates which chip edges are transmitting and which are receiving during this cycle. A value of 1 means that the North and West directions are driving; 0 means that South and East are driving. \section{Special Instructions} \subsubsection*{SARI: Set Address Register Immediate} Set the DRAM address register from the Block Address specified in the instruction. The address register is 20 bits wide, allowing up to 1 Megawords (each of 32 bits) to be addressed. Additional memory expansion is supported by use of the DRAM control lines as chip select. \begin{tabular}{|l|l|l|l|} \hline X & Block Address & 0010 & 00000000 \\ \hline \stopbit{32} & \bit{12} & \bit{8} & \bit{0} \\ \end{tabular} \subsubsection*{SARD: Set Address Register} Set the DRAM address register from the low bits of the Data Plane. \begin{tabular}{|l|l|l|l|} \hline X & 0110 & 00000000 \\ \hline \stopbit{12} & \bit{8} & \bit{0} \\ \end{tabular} \subsubsection*{LCR: Load Control Regs} \begin{tabular}{|l|l|l|l|l|} \hline X & Control Bits & Mode & 1100 & 00000000 \\ \hline \stopbit{21} & \bit{20-16} & \bit{15-12} & \bit{8} & \bit{0} \\ \end{tabular} Load a set of control registers from the data word. The new setting takes effect at the start of the next cycle. There needs to be an additional control register to individually select the high or low DRAM bank. \begin{center} \begin{tabular}{|r|l|l|} \hline \hdr{Bit} & \hdr{Name} & \hdr{Description} \\ \hline 20 & DRAM Chip Select 1 & DRAM chip select \\ \hline 19 & DRAM Chip Select 0 & DRAM chip select \\ \hline 18 & DRAM Hold 1 & DRAM holdstate, upper 32 \\ \hline 17 & DRAM Hold 0 & DRAM hold state, lower 32 \\ \hline 16 & Grid Bypass & Global OR pad latch enable \\ \hline \end{tabular} \end{center} The two DRAM select registers are a power-saving mode which avoid toggling the buffers. There are two registers in case only one SIMM was used. The mode field controls how the control bit field affects the control register. With four mode bits, all operations on the regs are possible. For example, four useful operations are below. \begin{center} \begin{tabular}{|l|l|} \hline \hdr{Mask} & \hdr{Operation} \\ \hline 1100 & Copy \\ \hline 1111 & Set \\ \hline 0000 & Clear \\ \hline 0101 & Toggle \\ \hline \end{tabular} \end{center} \subsubsection*{LI: Load Immediate} \begin{tabular}{|l|l|l|l|l|l|} \hline Constant (31-8) & Dest Address & Constant (7-0) & 01 & 00000000 \\ \hline \stopbit{23} & \bit{22-18} & \bit{17-10} & \bit{8} & \bit{0} \\ \end{tabular} Write the specified constant into the specified register in the left memory bank. The constant field is split up to simplify decoding (note that the write address is in the same location as in the regular instruction). To execute this instruction via the TAP interface, drive the literal bus values to the \emph{inverse} of the desired bit pattern, and execute a \texttt{clear} operation on the left ALU. All PE columns receiving a literal 0 will produce a 1 on the ALU output; columns receiving a literal 1, will pass the ALU output unchanged. Thus, a \texttt{clear} will store a 0 in columns with a literal 1. \subsubsection*{LIO: Load From IO Port} \begin{tabular}{|l|l|l|l|l|} \hline X & Advance Plane & UpdateReg? & 1010 & 00000000 \\ \hline \stopbit{14} & \bit{13} & \bit{12} & \bit{8} & \bit{0} \\ \end{tabular} Load either the upper or lower 16 bits of the IO plane input with the contents of the IO port. The {\tt HalfWord} bit specifies upper (set) or lower (clear) half. Optionally advance the IO plane. Another bit in this instruction disables this operation. The effect is to allow IO plane advancing without affecting the state of the latches. \subsubsection*{SIO: Store To IO Port} \begin{tabular}{|l|l|l|l|l|} \hline X & Advance Plane & UpdateReg? & 1110 & 00000000 \\ \hline \stopbit{14} & \bit{13} & \bit{12} & \bit{8} & \bit{0} \\ \end{tabular} Enable either the upper or lower 16 bits of the IO plane output with the contents of the IO port. The {\tt HalfWord} bit specifies upper (set) or lower (clear) half. Optionally advance the IO plane. Another bit in this instruction disables this operation. The effect is to allow IO plane advancing without affecting the state of the latches. \subsection{Timing Information} The timing bits for the DRAM interface are shown in \tab{dramtiming}. \begin{table}[htbp] \begin{center} \begin{tabular}{|r|l|l|} \hline \hdr{Bit} & \hdr{Name} & \hdr{Description} \\ \hline 60 & xWrite & Write clock. Cleared for NOPs\\ 59 & xNetPre & NetPrecharge control\\ 58 & Word Select & Determines whether upper or lower word latches are loaded\\ 57 & \z{RE}\dag & Row enable \\ 56 & \z{CAL}\dag & Column address latch \\ 55 & W/R\dag & Write/Read \\ 54 & \z{F}\dag & Refresh \\ 53 & \z{WE}\dag & Write Enable \\ 52 & \z{G}\dag & Output Enable\\ 51 & Row/Col & Row/column address select\\ 50 & Dload & DRAM Load signal for DRAM latch\\ 49 & Dstore & DRAM Store signal for DRAM latch\\ 48 & DPClk & DP Clock: advance data plane\\ 47 & AddrInc & Addr increment: advance address counter\\ \hline \end{tabular} \end{center} \caption{DRAM Timing Information\label{tab:dramtiming}} \end{table} Instruction bits marked with a dagger (\dag) are destined for the DRAM control wires. Refer to the Ramtron specification sheet for a description. Note that the {\tt S} control line is driven from a configuration register. {\bf Row/Col} selects whether the 11-bit row address or the 9-bit column address is enabled onto the address pins. {\bf DPClk} selects whether data plane advances. {\bf AddrInc} selects whether the column address is incremented. % Local Variables: % mode: latex % TeX-master: "main" % End: