%* Last edited: Sep 5 17:34 1996 (misha) \section{Testing the Chip} This section describes the methodology and results of testing the chip. Its primary purpose is to document the testing environment to validate the test measurements. The test setup consisted of four hardware and software modules: the test board itself, a clock driver, a scan controller, and a Sun workstation. The test chip was mounted on the test board described earlier. The clock was provided by a clock board which was essentially an ECL flip flop in a divide-by-two configuration connected to an oscillator socket. The socket was driven by an ECL-level oscillator or a waveform generator for high and low-speed tests, respectively. The flip-flop ensured that the clock duty cycle would be close to 50\%. The scan controller was a DSP board based on the TI C30 processor. The controller interfaced with the test board through a four-wire CMOS-level IEEE TAP interface. A Sun workstation communicated with the controller through a conventional RS-232 interface. \subsection{Test Board} The test board consisted of 12 layers, as described in \tab{stackup}. As well as testing the chip, designing the board served to demonstrate that routing of the fairly wide busses, both instruction and \mesh, was possible. The routed single-chip wiring can easily be replicated as a macro route multi-chip boards. Six signal layers proved sufficient to route all signals. The test board also demonstrated that PCB design software was able to route differential ECL signals well.\footnote{Whee! --Carlin} The board wiring methodology was controlled impedance {\em offset stripline\/}, with horizontal and vertical pairs of routing between two power or ground planes. These planes isolated the layers, and the orthogonal orientation between the planes ensured that signals within the same ground plane pair did not couple over long distances. The board accepted four separate power supplies. Even though the ECL circuits were operated at CMOS levels in offset mode, between 0 and 5 volts, instead of -5.2~V and 0~V, the board also included a 3~V termination voltage plane, and a 1~V \mesh\ signalling plane. \begin{Table}{stackup}{Board Stackup}{Board Stackup} \begin{tabular}{|r|l|l|l|} \hline Layer & Name & Orientation & Purpose \\ \hline 1 &TOP & Random & SMT/via connectors. \\ 2 &$V_{TT}$ & Plane & ECL termination voltage. Tied to 2V.\\ 3 &X1 & Horizontal & Routing\\ 4 &Y1 & Vertical & Routing\\ 5 &$V_{CC}$ & Plane & Positive power supply. Tied to 5V.\\ 6 &X2 & Horizontal & Routing\\ 7 &Y2 & Vertical & Routing\\ 8 &$V_{EE}$ & Plane & Negative power supply. Tied to 0V.\\ 9 &X3 & Horizontal & Routing\\ 10 &Y3 & Vertical & Routing\\ 11 &$V_{CE}$ & Plane & 1 V power supply. Tied to 1V.\\ 12 &BOT & Plane & Negative power supply. Tied to 0V.\\ \hline \end{tabular} \end{Table} The top and bottom layers of the PC board were not used for wiring. The bottom was unused because the dense wiring area around the PE chip was covered by the interposer clamp block. %Differential signals: Chip I/O, clock, global OR, length matched, run %adjacent. Capacitance is increased, but whatever affects one trace, affects %the other trace. %% Terminations and such. Scope specifications. \subsection{Test Process} The chip was tested through the Test Access Port (TAP) interface as follows: \begin{enumerate} \item The user writes a C-based test program on the Sun workstation using calls to the Abacus assembler library. \item The test program runs on the Sparc and generates a driver C program targeted for the DSP board. \item The user downloads the driver object code to the DSP board. \item The driver runs on the DSP board and uses the C30 digital I/O ports to control the TAP interface on the Abacus chip. \end{enumerate} The clock board was driven by one of two crystals, either 200 MHz or 160 MHz, or a waveform generator with a maximum frequency of approximately 25 MHz. Since the clock board divided the clock by two, the resulting chip test speed was either 100, 80, or 12.5 MHz. \subsection{Test Results} All data shown in this section was obtained with a Tektronix TDS 460 digital sampling oscilloscope. The probes were custom low-capacitance 21:1 shop probes made with a 1 K$\Omega$ isolating resistor and RT58 coax cable. \paragraph{Heartbeat monitor.} The first test was to ensure that the differential ECL clock signal was received properly and reached the on-chip timing generator. One of the four debug pins output a copy of the {\tt Read} clock taken from the eastern edge of the PE array. This 3.3~ns pulse is shown in \fig{clockread}. As expected, the pulse occurs a fixed amount of time after the rising clock edge and is not affected by the duration of the clock period. \mypsfigy{2.75in}{clock_read.ps}{clockread}{Read Clock Monitor}{ The heartbeat monitor: a copy of the read clock.} \paragraph{TAP Interface.} The next testing step was to communicate with the TAP interface. \fig{tap} shows the output of the serial {\em TDO\/} (TAP Data Out) pin after the reset signal was asserted. This test demonstrated that the TAP was functional and that further testing could proceed. \mypsfigy{2.75in}{tap.ps}{tap}{TAP Interface}{ TAP Interface} \paragraph{IO Burst.} A bit pattern was loaded into the top PE row with the literal load command. It was then transferred to the IO plane, and then to the output register. Finally, the IO burst was enabled to produce the waveform shown in \fig{ioburst}. The specific bit pattern is 0xFF30A7. The pattern is reversed, since the LSB appears first on the output of the scope. The ground/supply voltage bounce is about 200 mV. Although only a single- ended trace is shown in the figure, the output is driven differentially, eliminating the common-mode bounce. \mypsfigy{2.75in}{ioburst100.ps}{ioburst}{IO Burst}{ Output Burst Trace, 100 MHz. } \paragraph{Data Plane Shift.} The next test involved testing the operation of the data plane. The DP register was set high, and then the data plane shifting was enabled. The DRAM I/O pins floated low, so that a zero propagated through the data plane as shown in \fig{dpshift}. As expected, after thirty-two cycles, the zero appeared at the top row. For this test, the global OR output pin was used, testing both subsystems. \mypsfigy{2.75in}{dpshifdt100.epsi}{dpshift}{DP Shift}{ Data plane toggle at 100 MHz. The data plane is loaded with 1s. A zero is then introduced at the input. 32 cycles later the 0 is has been shifted through. } \paragraph{External Memory Pads.} The DRAM pads were toggled at 100 MHz. \mypsfigy{2.75in}{dramtogglefastB80.ps}{dramtoggle}{DRAM toggle at 80}{ DRAM pads were designed to toggle at only 62.5 MHz.} \paragraph{Register File Toggle.} The next test showed the first failure of the chip. The repeated instruction was very simple: toggle a memory bit and copy it onto the burst output pin. This operation started failing at 80~MHz. Instead of a pattern of alternating zeroes and ones, the pin showed two high values followed by a low. \begin{Figure}{iotoggle}{IO Toggle}{IO Toggle} \leavevmode \epsfysize 2.75in \epsffile{\mypsdirectory toggleioB20.ps} \vspace{1ex} \epsfysize 2.75in \epsffile{\mypsdirectory toggleioB80.ps} \vspace{1ex} \epsfysize 2.75in\epsffile{\mypsdirectory toggleioB100.ps} \vspace{1ex} \end{Figure} %\mypsfigy{2in}{toggleioB20.ps}{toggle20}{IO Toggle, 20 MHz}{ % Memory toggle at 20 MHz} %\mypsfigy{2in}{toggleioB80.ps}{toggle80}{IO Toggle, 80 MHz}{ %Memory toggle at 80 MHz. Incipient failure} %\mypsfigy{2in}{toggleioB100.ps}{toggle100}{IO Toggle, 100 MHz}{ %Memory toggle at 100 MHz. Failure occurs.} \paragraph{\Mesh\ Shift Operation.} The on-chip \mesh\ communication was tested next. As shown in \fig{gridshift}, the pattern was shifted out. Although only 20~MHz operation is shown, the \mesh\ shifting worked at 80~MHz, and failed (by shifting incorrect data) at 100~MHz. \mypsfigy{2.75in}{gridfastscope.ps}{gridshift}{\Mesh\ Shift}{ \Mesh\ shifting at clock rate. Only the 20 MHz operation is shown.} \subsection{Testing Summary} \begin{Table}{testsummary}{Testing Summary}{Testing Summary} \begin{tabular}{|l|l|} \hline Subsystem & Status \\ \hline Burst Output & Operational at 100 MHz \\ Internal Memory toggle & Operational at 80 MHz\\ On-chip \mesh\ communication & Operational at 80 MHz\\ Data Plane shift & Operational at 100 MHz\\ TAP interface & Fully operational\\ \hline \end{tabular} \end{Table}