        HP CMOS26B SPICE Model Calibration Data For Outside Customers

                            September 21, 1992


Peter M. O'Neill
Hewlett-Packard Co.
Integrated Circuit Business Div.
Fort Collins, Co.
Phone: 303-229-4562
Internet: peteo@fc.hp.com

INTRODUCTION

This application note provides the information necessary for CMOS26B designers
outside of Hewlett-Packard Co. to verify that the HSPICE Level 28 models we
have provided are working properly in the customer's simulation environment.
Reference is made in each section to the corresponding HSPICE circuit files
provided with this note.  External customers who have a proprietary simulator
or who insist on using HSPICE models other than the Level 28 modified BSIM may
also find this information usefull in doing their own model fitting.  The
results presented here are based on simulations with HPSPICE, the proprietary
SPICE simulator used within Hewlett-Packard, and measurements.

BASIC TRANSISTOR I-V

Idsat versus drawn channel length for slow, nominal, and fast process cases.
Idsat is the drain current at Vds=Vgs=5.0V.  "L" refers to the drawn channel
the way HP draws it with the minimum length being 1.00um.  Can be simulated
with circuit files nsat.cki and psat.cki.

		Idsat for W=20um @ 30C in mA.
	L	Slow	Nom	Fast	Slow/Nom  Fast/Nom  Slow/Fast
        ----    ----    ---     ----    --------  --------  ---------
	NMOS
	 1.0	7.50	8.70	9.78	.86	    1.12	1.30
	 1.1	7.32	8.44	9.44	.87	    1.12	1.29
	 1.2	6.73	7.72	8.62	.87	    1.12	1.28
	 3.0	3.43	3.81	4.17	.90	    1.09	1.22
	 5	2.10	2.30	2.50	.91	    1.09	1.19
	10	1.06	1.15	1.24	.92	    1.08	1.17
	20	0.544	0.588	0.632	.93	    1.08	1.16
	1.6/1.0	0.399	0.500	0.610	.798	    1.220	1.529

	PMOS
	 1.0	3.13	4.04	4.91	.772	    1.218	1.58
	 1.1	2.88	3.67	4.44	.783	    1.212	1.55 
	 1.2	2.64	3.32	4.00	.791	    1.206	1.52
	 3.0	0.966	1.125	1.317	.855	    1.170	1.37
	 5	0.560	0.639	0.743	.878	    1.163	1.32
	10	0.282	0.317	0.367	.890	    1.154	1.30
	20	0.136	0.152	0.175	.910	    1.151	1.28
	1.6/1.0	0.155	0.210	0.278	.741	    1.327	1.789

MODEL-INDEPENDENT TRANSISTOR PARAMETERS

Values for the "physical" parameters that should be equivalent in most FET
models.

	Parm	      Units	Slow	Nom	Fast
        ----          -----     ----    ---     ----
	NMOS
	Long Vtx	V	.759	.700	.654
	Uo	      cm2/V*S	499	505	511
	Tox		nm	17.1	16.6	16.1
	Ld		nm	150	193	220
	Leffective	um	.700	.614	.560
	Wd		nm	293	250	198
	Cgd,Cgs	      aF/um	200	190	181
	Cj	      aF/um2	168	160	152
	Cjsw	      aF/um	535	510	485
	Mj	        -	 -	.425     -
	Mjsw            -	 -	.290     -
	Pb		V        -	.27	 -
	Pbsw		V	 -	.45	 -
	Rsdw	      Ohm*um	 -	380	 -
	20/20 Beta     uA2/V	   99	  104	  110
	20/1  Beta     uA2/V    2,790   3,340   3,840

	PMOS
	Long Vtx	V	-.986   -.900   -.857
	Uo	      cm2/V*S	155     160     174
	Tox		nm	17.1	16.6	16.1
	Ld		nm	100	169	196
	Leffective	um	.800	.662	.608
	Wd		nm	331	310	263
	Cgd,Cgs	      aF/um	284	270	256
	Cj	      aF/um2	704	670	636
	Cjsw	      aF/um	331	315	299
	Mj	        -	 -	.460	 -
	Mjsw            -	 -	.225	 -
	Pb		V	 -	.78	 -
	Pbsw		V	 -	.42	 -
	Rsdw	      Ohm*um	 -	850	 -
	20/20 Beta    uA2/V      31       33      37
        20/1  Beta    uA2/V     757      974   1,200

Long Vtx is the extrapolated threshold of a long channel FET.  We measure it as
the voltage axis intersection of the line tangent to the point of maximum slope
of the Id vs. Vgs curve at Vds=30mV and Vbs=0.

Please note that these are neither the control limits nor the scrap limits.
In the case of the DC parameters, they are merely the values needed to match
the scrap limits of the saturation current (Id @ Vgs=Vds=5.0V, Vbs=0)
distribution as scaled from standard CMOS26.  The capacitances were skewed from
nominal by a simple +/-5%.  

Note that while CMOS26B is specified as a 16.0nm gate oxide process the nominal
gate oxide thickness given above is 16.6nm.  The gate oxide thickness as
measured optically in fabrication

N 16.0nm but this translates into 16.6nm
measured capacitively using a relative permittivity of 3.9

N defined by
SPICE.

TIMING

Timing can be verified with the simple ring oscillator rosc4.cki that
has seven stages, each stage being composed of two N and two P FETs all in
series so

N to exhibit backgate effect on the inner two FETs.  The simulations
were done in Hewlett-Packard's internal simulator, HPspice which is our
accepted standard, at 5V and 30 degrees C with the slow, nominal, and fast
cases.  The results reported are the propagation delay, period of oscillation
divided by twice the number of stages, in picoseconds.

                        Case            Prop. delay in pS
                        ----            -----------------
                        Fast                    226.6
                        Nominal                 278.4
                        Slow                    369.6

We have found that the Hspice Level 28 models that we provide predict about 5%
less delay than HPspice.

NMOS TO PMOS MATCHING

We quantify the NMOS to PMOS transistor matching with the logic threshold of a
simple inverter inv.cki.  The inverter composed of 1.6/1.0 N and P FETs, has
min., nom., and max. values of the Vout=Vin point of 1.75, 1.92, and 2.12V. 
This can be modeled by deviating the threshold voltages by the following
amounts:

		Leftmost Xfer	Rightmost Xfer
                ------------    --------------
	N	    -.069	  +.089
        P	    -.129	  +.064

TRANSISTOR TEMPERATURE EFFECTS

I generated CMOS26B temperature effect models by perturbing my earlier 30C
models.  I did this by first determining the major temperature effects over
channel length according to direct measurements or simple, unambiguous
parameter extractions.  Since the FET arrays that I measured over the
temperature range were not the same

N the nominal, slow, or fast model cases,
I expressed these temperature effects

N temperature coefficients of either a
difference per degree of temperature or a fractional difference per degree as
dictated by some physical reasoning. I then adjusted the detailed SPICE model
parameters of the nominal case for the simulations to match these temperature
coefficients while maintaining I-V curve shapes as close as possible to those
measured over temperature.  I used the same
parameter skewing as at 30C to
handle the process spread at the other temperatures.

I did my measurements at -14, 0, 30, 60, 85, and 110C.  I found that Idsat, Id
at Vgs= Vds=5.0V and Vbs=0, is described roughly by a (Delta %)/(Degree C) that
decreases with decreasing channel length due to increasing carrier velocity
saturation, but it is actually nonlinear so I have described it by a table.
Extrapolated threshold at both 0 and 5V of backgate, Vt0 and Vt5 respectively,
decrease in magnitude with increasing temperature as a temp. co. in mV/C.  For
more specific effects I found that low field mobility U0 follows the classic
power law but not with the classic power of -1.5 and that, only in the NMOS,
the source/drain resistance has a classic temperatute coefficient for a
diffused resistor.  I summarize my results below so
that you may use them in
addition
to the original 30C process spread information that I have given
above.

			N Channel FETs

Saturation current:  [Idsat(T) - Idsat(To)]/[Idsat(To)*(T - To)] = A

Named Length in um      1.0    1.1    1.2    1.5    3      5      10     20
Temp. Coef. A in %/C   -.191  -.204  -.213  -.238  -.311  -.351  -.376  -.386

      NMOS Idsat Normalized to 30C, Smoothed
              Length (um), W=20um
   Temp      1.0    1.1    1.2    1.5    3.0    5.0   10.0   20.0
    110    0.847  0.837  0.830  0.811  0.751  0.719  0.699
 0.691
     85       NA     NA     NA     NA     NA     NA     NA     NA
     60    0.939     NA     NA     NA     NA     NA     NA  0.862
     30    1.000  1.000  1.000  1.000  1.000  1.000  1.000  1.000
      0    1.063  1.074  1.078  1.084  1.117  1.139  1.155  1.150
    -14    1.095  1.113  1.116  1.121  1.177  1.211  1.239  1.238

Threshold voltages:  (Vt(T) - Vt(To))/(T - To) = B
                     For Vt0, B = -1.34mV/C independent of L
                     For Vt5, B = -0.72mV/C independent of L

Low field mobility:  Uo(T)/Uo(To) = (T/To)^C
                     C = -1.69

Source/Drain resistance:  [Rsdw(T) - Rsdw(To)]/[Rsdw(To)*(T - To)] = D
                          D = .0041/C


			P Channel FETs

Saturation
current:  (|Idsat(T)| - |Idsat(To)|)/[|Idsat(To)|*(T - To)] = A

Named Length in um	1.0    1.1    1.2    1.5    3      5      10     20
Temp. Coef. A in %/C   -.134  -.145  -.155  -.175  -.223  -.240  -.254  -.256

        PMOS Idsat Normalized to 30C, Smoothed
                       Length (um), W=20um
          Temp (C)    1.0    1.1    1.2    1.5    3.0    5.0   10.0
              110   0.893  0.884  0.876  0.860  0.822  0.808  0.797
               85   0.924  0.913  0.909
 0.891  0.857     NA     NA
               60   0.958  0.950  0.943  0.937  0.915     NA     NA
               30   1.000  1.000  1.000  1.000  1.000  1.000  1.000
                0   1.043  1.048  1.052  1.065  1.081  1.098  1.108
              -14   1.064  1.074  1.084  1.102  1.143  1.162  1.172

Threshold voltages:  (Vt(T) - Vt(To))/(T - To) = B
                     For Vt0, B = 1.78mV/C independent of L
                     For Vt5, B = 1.25mV/C independent of L

Low field mobility:  Uo(T)/Uo(To) = (T/To)^C
                     C = -1.17

Source/Drain resistance: No temperature effect for the Rsdw that is extracted
			 for PMOS.

Propagation delay increases about .24% per degree C.

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