Stephen W. Keckler
Massachusetts Institute of Technology


		    The M-Machine Multicomputer

Advances in VLSI technology have resulted in computers with chip area
dominated by memory and not by processing resources.  A 64-bit
processor with a pipelined FPU is only 8% of a 1996 0.35um chip.  In a
system with 256 MBytes of DRAM, the processor accounts for only 0.13%
of the silicon area in the system.  The memory system, cache, TLB,
controllers, and DRAM account for most of the remaining area.
Technology scaling has made the memory, rather than the processor, the
most area-consuming resource in a computer system.

This talk presents the MIT M-Machine, an experimental multicomputer
being designed and built to test architectural concepts motivated by
the constraints of modern semiconductor technology and the demands of
programming systems.  The M-Machine computing nodes are connected via
a 3-D mesh network; each node consists of a custom 13 million
transistor Multi-ALU processor (MAP chip) and 8 MBytes of off-chip
synchronous DRAM.  The MAP chip incorporates 12 function units, an
interleaved on-chip cache, network interface, and a 3-D dimension
ordered router.  For a 32 node 256MB M-Machine, the peak
performance/area is 85 times better than today's microprocessor based
systems at only 50% more silicon area cost.  Even at a small fraction
of this peak performance, the M-Machine will allow the costly,
fixed-sized memory to handle more problems per unit time resulting in
more cost-effective computing.

In order to achieve the speedup required, the MAP chip employs
mechanisms that enable parallelism within each node and across nodes,
including instruction level parallelism, multithreading, fast user
level messaging, and transparent access to remote memory.  This talk
will focus on the novel mechanisms of the MAP chip, the compilation
model for executing code on a single node, and on some implementation
issues that arise when building a large, complex chip in a university
environment.
