Calculations of expected capacitances for capacitive pads:

The area of the standard pad is 750 microns x 125 microns, or 93750
square microns.  Calculate the expected capacitance to an electrode 10
microns above the surface, with K = 30, with a .6 micron silicon
nitride scratch protection K = 7 and .4 micron overglass K = 4.

C = KeA/t = 30 x 8.85e-14 F/cm x 9.4e-4 cm**2 / 1e-3 cm = 2.35 pF

             7 x 8.85e-14      x 9.4e-4       / .6e-4   = 9.7 pF

             4 x 8.85e-14      x 9.4e-4       / .4e-4   = 8.3 pF

Ctotal = 1/(1/C1 + 1/C2 + 1/C3) = 1.54 pF

Parasitic capacitance: 3.5 microns of K = 4 under M3 pads.

C =          4 x 8.85e-14      x 9.4e-4       / 3.5e-4  = .95 pF




With a K = 80 dielectric (water) and a 1 micron gap the capacitance
will be 

C =         80 x 8.85e-14      x 9.4e-4       / 1e-4 = 66.5 pF

Ctotal including overglass and scratch:

Ctotal = 66.5 || 9.7 || 8.3 = 4.19 pF

Summary: pad capacitances range from 1.5 to 4 pF, determined largely
by the overglass thickness and dielectric constant, rather than by the
dielectric material, for plausible values.

Parasitic capacitances of the pad to structures underneath are about
1 pF, assuming we have no metal-1 or metal-2 conductors under the
pads.

The simulations will be done for parasitic capactances of 1 pF, and
for a variable coupling capacitance of between 1 and 5 pF.



Input Protection Layout:

Special design rules for large contacts in protection devices:

Contacts  (m1 to dif) may be 2.0 microns wide by as long as desired.
Large contacts must be surrounded by 1.0 microns of metal-1 and 1.8
microns of diffusion.

Diffusion must have rounded corners or stairstepped diagonal corners.

Protection device consists of N-dif in substrate tied to the input,
separated from N-dif in substrate tied to ground by a 1.0 micron gap.

Input protection resistor:

The input protection resistor will consist of a 3.0 micron drawn (2.8
micron effective) wide N-dif region, consisting of 67 squares, i.e.
187 microns of length.  The resistor will have rounded corners as for
the layout of the primary protection device.

Guard ring layout.

The protection device and resistor will be entirely surrounded by a
guard ring, consisting of two concentric rings.  The inner ring
consists of an N-well 30 microns wide, filled with N-Dif, and densely
contacted with metal-1.  This ring is tied to Vdd.  This structure
looks like a very large well contact in the N-well.

The outer ring consists of a P-dif region 30 microns wide densely
contacted in metal-1.  The metal-1 is tied to ground.  This structure
looks like a very large substrate contact in the P substrate.



I still want a reading on the electrical drive capability of the input
pads that you come up with.  Also, what is the pad pitch of these
pads.


Please do not omit the substrate and well contacts while doing the
layout (!).  The more the merrier, but we need one at least every 100
microns in regions with devices.